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参数资料
| 型号： | CY28508OXCT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK SSCG 3DIFF PAIR 28SSOP |
| 标准包装： | 1,000 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 333.3MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
CY28508
........................ Document #: 38-07534 Rev. *F Page 5 of 13
Byte 3: Dial-a-Frequency Control Register N1 [default = 224.70 MHz, N = 86d, ODSEL = 1]
Bit
@Pup
Description
7
0
Reserved, set = 0.
61
N6, MSB
50
N5
41
N4
30
N3
21
N2
11
N1
00
N0, LSB
Byte 4: Dial-a-Frequency Control Register M1 [default = 224.70 MHz, M = 49d, ODSEL = 1]
Bit
@Pup
Description
7
1
Reserved, set = 1.
6
1
SWODSEL: Output divider select. 0 = /2, 1 = /3.
Changing the output divider causes large instantaneous changes in the CPU pulse width and
should only be changed before system operation is to occur.
5
1
M5 MSB.
41
M4
30
M3
20
M2
10
M1
0
1
M0, LSB.
Byte 5: Dial-a-Frequency Control Register N2 – Only Bit 7 is Used by the CY28508
Bit
@Pup
Description
7
0
UP/DN pulse width limit. During Smooth-Track, the bandwidth hence the slew rate is controlled through
limiting the pulse width of the UP/DN pulse outputs of the phase detector going to the charge pump. The
default is 0 = 20 ns and can be programmed to 1 = 40 ns, which will increase the slew rate.
6
0
Reserved, set = 0.
5
1
Reserved, set = 1.
4
1
Reserved, set = 1.
3
0
Reserved, set = 0.
2
0
Reserved, set = 0.
1
0
Reserved, set = 0.
0
Reserved, set = 0.
Byte 6: Dial-a-Frequency Control Register M2 – Only Bits 6 and 7 are Used by the CY28508
Bit
@Pup
Description
7
1
FSEL Control: 1 = HW FSEL, 0 = SW FSEL
6
1
SW FSEL: 0 = SW MN0 select, 1 = SW MN1 select. Only valid when B6b7 = 0.
5
1
Reserved, set = 1.
4
1
Reserved, set = 1.
3
0
Reserved, set = 0.
2
0
Reserved, set = 0.
1
0
Reserved, set = 0.
0
Reserved, set = 0.
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