参数资料
型号: CY2CC1810
厂商: Cypress Semiconductor Corp.
英文描述: 1:10 Clock Fanout Buffer with Output Enable
中文描述: 1:10时钟扇出缓冲器的输出使能
文件页数: 5/8页
文件大小: 128K
代理商: CY2CC1810
COMLINK
SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 5 of 8
Parameter Measurement Information
:
V
DD
@ 3.3V
[10,12,13]
Notes:
10. C
includes probe and jig capacitance
11.
Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH, except when disabled by the output control.
12. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50
,
t
R
< 2.5 nS, t
F
< 2.5 nS.
13. The outputs are measured one at a time with one transition per measurement.
14. t
PLZ
and t
PHZ
are the same as t
DIS
.
15. t
and t
are the same as t
EN
.
16. tPLH and tPHL are the same as t
PD
.
From Output
Under Test
C
L
= 50 pF
500 ohm
V
SS
Open
2x VDD
500 ohm
Figure 6. Load Circuit
2.7 V
0 V
Input
t
w(20-80)
2.7 V
0 V
1.5 V
1.5 V
Input
t
w(50-50)
1.5 V
Figure 7. Voltage Waveforms
Pulse Duration
From Output
Under Test
C
L
= 3 pF
500 ohm
Figure 8. Point-to-Point Load Circuit
Table 2.
Test
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
2xVDD
VSS
See
Figure 9
See
Figure 10
1.5 V
1.5 V
1.5 V
1.5 V
t
PLH
t
PHL
1.5 V
V
OH
V
OL
0 V
Input
Output
Figure 9. Voltage Waveforms
Propagation Delay Times
[16]
Output Control
(low-level enabling)
Waveform 1
S1 at 2 x VDD
3 V
Waveform 2
S1 at GND
3.3 V
t
PLZ
t
PHZ
t
PZH
t
PZL
1.5 V
1.5V
0 V
~0 V
V
OL
+ 0.3V
V
OH
- 0.3V
V
OL
V
OH
Z
Z
1.5 V
VOH (min)
VOL
(max)
Figure 10. Voltage Waveforms
Enable and Disable Times
[11,14,15]
INPUT
OUTPUT
t
PLH
t
PHL
tsk
(P)
=
l
t
PHL
- t
PLH
l
3V
1.5V
0V
VOH
1.5V
VOL
Figure 11. Pulse Skew
tsk
(p)
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