1:10 Clock Fanout Buffer
COMLINK SERIES
CY2CC810
Cypress Semiconductor Corporation
Document #: 38-07056 Rev. *C
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
Features
Low-voltage operation
V
DD
range from 2.5V to 3.3V
1:10 fanout
Over voltage tolerant input hot swappable
Drives either a 50-Ohm or 75-Ohm transmission line
Low-input capacitance
Low-output skew
Low-propagation delay
Typical (tpd < 4 ns)
High-speed operation > 500 MHz
Industrial versions available
Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC810 fanout buffer features one input and
ten outputs. Designed for data communications clock
management applications, the large fanout from a single input
reduces loading on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance matching and eliminate the need for series
damping resistors; they also reduce noise overall.
Pin Description
Pin Number
Pin Name
IN
GND
V
DD
Q1... Q10
Description
1
2, 6, 10, 13, 17
4, 8, 15, 20
3, 5, 7, 9, 11, 12, 14, 16, 18, 19
Input
Ground
Power Supply
Output
LVCMOS
Power
Power
AVCMOS
Block Diagram
Pin Configuration
OUTPUT
(AVCMOS)
IN
Q1
Q5
Q7
Q6
Q4
Q3
Q2
Q8
Q9
Q10
GND
VDD
INPUT
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
C
20 pin SOIC/SSOP
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND