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参数资料
| 型号： | CY2DP314OIT |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | CAT5 VIDEO RS232 EXTENDERKIT |
| 中文描述： | 2DP SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | 5.30 MM, SSOP-20 |
| 文件页数： | 2/9页 |
| 文件大小： | 213K |
| 代理商： | CY2DP314OIT |
CY2DP314
Document #: 38-07550 Rev.*E
Page 2 of 9
Governing Agencies
The following agencies provide specifications that apply to the
CY2DP314. The agency name and relevant specification is
listed below in
Table 2
.
Pin Definitions
Pin
Name
I/O
Type
Description
1,10,11,20,3
2
4
5
6
7
8
9
18,16,14,12
19,17,15,13
VCC
NC
CLK_SEL
CLKA
CLKA#
CLKB
CLKB#
VEE
[2]
Q[0:3]#
Q[0:3]
+PWR
Power
Power supply, positive connection
No connect
InPut Clock Select
Default differential clock input
Default differential clock input
Alternate differential clock input
Alternate differential clock input
Power supply, negative connection
Complement output
True output
I,PD
I,PD
[1]
I, PD/PU
I,PD
I, PD/PU
–PWR
O
O
LVCMOS
ECL/PECL
ECL/PECL
HSTL
HSTL
Power
ECL/PECL
ECL/PECL
Table 1.
Control
CLK_SEL
0
Operation
CLKA, CLKA# input pair is active (Default condition with no connection to pin)
CLKA can be driven with ECL- or PECL-compatible signals with respective power configurations
CLKB, CLKB# input pair is active.
CLKB can be driven with HSTL-compatible signals with respective power configurations
1
Table 2.
Agency Name
JEDEC
Specification
JESD 020B (MSL)
JESD 8-6 (HSTL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
883E Method 1012.1 (Thermal Theta JC)
Mil-Spec
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), V
is either –3.3V or –2.5V and V
is connected to GND (0V). In PECL mode (positive power supply mode),
V
is connected to GND (0V) and V
CC
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
CC
)
and are between V
CC
and V
EE
.
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