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| 型号： | CY2SSTV857ZXI-32T |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC CLK DDR266/333BUF1:10 48TSSOP |
| 标准包装： | 2,000 |
| 系列： | * |
| 类型： | * |
| PLL： | * |
| 主要目的： | * |
| 输入： | * |
| 输出： | * |
| 电路数： | * |
| 比率 - 输入:输出： | * |
| 差分 - 输入:输出： | * |
| 频率 - 最大： | * |
| 电源电压： | * |
| 工作温度： | * |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
CY2SSTV857
.......................... Document #: 38-07557 Rev. *E Page 6 of 8
Absolute Maximum Conditions[2]
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ........... VDDQ + 0.3V
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:................................ –40°C to +85°C
Maximum Power Supply: ................................................ 3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDDQ.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDDQ).
DC Electrical Specifications[3]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VDDQ
Supply Voltage
Operating
2.375
–
2.625
V
VIL
Input Low Voltage
PD#
–
0.3 × VDDQ
V
VIH
Input High Voltage
0.7 × VDDQ
––
V
VID
Differential Input Voltage[4]
CLK, FBIN
0.36
–
VDDQ + 0.6
V
VIX
Differential Input Crossing
Voltage[5]
CLK, FBIN
(VDDQ/2) – 0.2 VDDQ/2 (VDDQ/2) + 0.2
V
IIN
Input Current [CLK, FBIN, PD#] VIN = 0V or VIN = VDDQ
–10
–
10
A
IOL
Output Low Current
VDDQ = 2.375V, VOUT = 1.2V
26
35
–
mA
IOH
Output High Current
VDDQ = 2.375V, VOUT = 1V
28
–32
–
mA
VOL
Output Low Voltage
VDDQ= 2.375V, IOL = 12 mA
–
0.6
V
VOH
Output High Voltage
VDDQ = 2.375V, IOH = –12 mA
1.7
–
V
VOUT
Output Voltage Swing[6]
1.1
–
VDDQ – 0.4
V
VOC
Output Crossing Voltage[7]
(VDDQ/2) – 0.2 VDDQ/2 (VDDQ/2) + 0.2
V
IOZ
High-Impedance Output Current VO = GND or VO = VDDQ
–10
–
10
A
IDDQ
Dynamic Supply Current[8]
All VDDQ, FO = 200 MHz
–
235
300
mA
IDD
PLL Supply Current
VDDA only
–
9
12
mA
IDDS
Standby Supply Current
PD# = 0 and CLK/CLK# = 0 MHz
–
100
A
Cin
Input Pin Capacitance
2
–
3.5
pF
AC Electrical Specifications [9, 10]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fCLK
Operating Clock Frequency
AVDD, VDDQ = 2.6V 0.1V
60
–
230
MHz
tDC
Input Clock Duty Cycle
40
–
60
%
tLOCK
Maximum PLL Lock Time
–
100
s
DTYC
Duty Cycle[11]
60 MHz to 100 MHz
49
50
51
%
101 MHz to 170 MHz
48
–
52
%
tsl(o)
Output Clocks Slew Rate
20%–80% of VOD
1
2
V/ns
tPZL, tPZH
Output Enable Time[12] (all outputs)
–
3
25
ns
tPLZ, tPHZ
Output Disable Time[12] (all outputs)
–
3
8
ns
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Unused inputs must be held HIGH or LOW to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage VTR–VCPI required for switching, where VTR is the true input level and VCP is the complementary
input level. See Figure 6.
5. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signal must be crossing.
6. For load conditions see Figure 6.
7. The value of VOC is expected to be (VTR + VCP)/2. In case of each clock directly terminated by a 120
resistor. See Figure 6.
8. All outputs switching load with 14 pF in 60
environment. See Figure 6.
9. Parameters are guaranteed by design and characterization. Not 100% tested in production.
10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 50 kHz with a down
spread or –0.5%.
11. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = tWHC/tC,
where the cycle time(tC) decreases as the frequency goes up.
12. Refers to transition of non-inverting output.
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