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| 型号： | CY39050Z676-125MGC |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件页数： | 16/86页 |
| 文件大小： | 1235K |
| 代理商： | CY39050Z676-125MGC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 16 of 86
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
(39K200, 208 EQFP) .................................–45
°
C to +125
°
C
Storage Temperature
(all other densities and packages)..............–65
°
C to +150
°
C
Soldering Temperature.................................................220
°
C
Ambient Temperature with
Power Applied...............................................–40
°
C to +85
°
C
Operating Range
Junction Temperature...................................................135°C
V
CC
to Ground Potential...................................–0.5V to 4.6V
V
CCIO
to Ground Potential................................–0.5V to 4.6V
DC Voltage Applied to Outputs
in High-Z state..................................................–0.5V to 4.5V
DC Input voltage...............................................–0.5V to 4.5V
DC Current into Outputs........................................± 20 mA
[6]
Static Discharge Voltage
(per JEDEC EIA./JESD22–A114A)............................>2001V
Latch-up Current .....................................................>200 mA
Note:
6.
7.
DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV, and 36 mA with GTL+ (with 25W pull-up resistor and V
= 1.5).
Input Leakage current is ±10
μ
A for all the pins on all the Delta39K package except the following pins in Delta39K100 packages: The input leakage current spec
for these pins in ±200
μ
A
Delta39K100
Package
388-BGA
484-FBGA
676-FBGA
8.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
= 0.5V has been chosen to avoid test
problems caused by tester-ground degradation. Tested initially and after any design or process changes that may affect these parameters.
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
Junction
Temperature
0
°
C to +85
°
C
Output
Condition
3.3V
2.5V
1.8V
1.5V
3.3V
2.5V
1.8V
1.5V
V
CCIO
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V
[5]
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V
[5]
V
CC
V
CCJTAG
/
V
CCCNFG
Same as
V
CCIO
V
CCPLL
V
CCPRG
Same as
V
CC
3.3V ± 0.3V or
2.5V ± 0.2V
(39KV)
3.3V ±
0.3V
Industrial
–40
°
C to +85°C
–40
°
C to +100°C
DC Characteristics
Parameter
V
DRINT
Description
Test
Conditions
V
CCIO
= 3.3V V
CCIO
= 2.5V
Min.
Max.
1.5
V
CCIO
= 1.8V
Min.
1.5
Unit
V
Min.
1.5
Max.
Max.
Data Retention V
CC
Voltage
(config data may be lost below this)
Data Retention V
CCIO
Voltage
(config data may be lost below this)
Input Leakage Current
Output Leakage Current
V
DRIO
1.2
1.2
1.2
V
I
IX[7]
I
OZ
GND
≤
V
I
≤
3.6V
GND
≤
V
O
≤
V
CCIO
V
CCIO
= Max.
V
OUT
= 0.5V
–10
–10
10
10
–10
–10
10
10
–10
–10
10
10
μA
μA
I
OS[8]
Output Short Circuit Current
–160
–160
–160
μA
I
BHL
Input Bus Hold LOW Sustaining Current V
CC
= Min.
V
PIN
= V
IL
+40
+30
+25
μA
I
BHH
Input Bus Hold HIGH Sustaining Current V
CC
= Min.
V
PIN
= V
IH
–40
–30
–25
μA
I
BHLO
I
BHHO
I
CC0
Input Bus Hold LOW Overdrive Current V
CC
= Max.
Input Bus Hold HIGH Overdrive Current V
CC
= Max.
Standby Current
+250
–250
All bins
20
20
30
60
60
+200
–200
All bins
20
20
30
60
60
+150
–150
μA
μA
μA
39K30
39K50
39K100
39K165
39K200
–125 bin
3
3
5
10
10
–83 bin
12
12
20
40
40
Pins
B4, C2
B8, G9
F11, J11
相关PDF资料 |
PDF描述 |
|---|---|
| CY39050Z676-125MGI | CPLDs at FPGA Densities |
| CY39050Z676-125NC | CPLDs at FPGA Densities |
| CY39050Z676-125NI | CPLDs at FPGA Densities |
| CY39050Z676-125NTC | CPLDs at FPGA Densities |
| CY39050Z676-125NTI | CPLDs at FPGA Densities |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39100V208-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125BBI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125BGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125BGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125MBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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