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| 型号： | CY39200V256-200NTC |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件页数： | 86/86页 |
| 文件大小： | 1235K |
| 代理商： | CY39200V256-200NTC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 86 of 86
Document History Page
Document Title: Delta39K ISR CPLD Family CPLDs at FPGA Densities
Document Number: 38-03039
Issue
Date
Change
**
106503
05/30/01
SZV
*A
107625
07/11/01
RN
REV.
ECN NO.
Orig. of
Description of Change
Change from Spec #: 38-00830 to 38-03039
Deleted 39K15 device and the associated -250-MHz bin specs
Deleted 144FBGA package and associated part numbers
Changed ESD spec from “MIL-STD-883” to “JEDEC EIA/JESD22-A114-A”
Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz”
Changed the part ordering information accordingly
Updated the -233-MHz timing specs to match modified timing specs achieved by
design (main affected params: t
PD
, t
MCCO
, t
IOS
, t
SCS
, t
SCS2
, f
MAX2
, t
CLMAA
,
t
CLMCYC2
, t
CHMCYC2
, t
CHMCLK
)
Updated I/O standard Timing Delay Specs and changed the default I/O standard
from 3.3V PCI to LVCMOS
Added paragraph about Delta39K being CompactPCI hot swap Ready
Added X8 mode in the PLL description
Added Standby ICC spec
Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead
of CY3LV020
Updated Delta39K family offering
Modified PLL timing parameters t
DWSA
, t
DWOSA
, t
MCCJ
, and t
LOCK
. Added t
INDUTY
parameter
Deleted exception to CompactPCI Hot Swap compliance regarding “PCI
buffers....”
Added reference to app note “Hot Socketing Delta39K”
Revised CompactPCI Hot Swap Specification R1.0 to be R2.0
Combined with spec# 38-03040
Updated pin tables for 39K30 (208PQFP, 256FBGA)
Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA)
Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL
Added PLL parameters (f
PLLVCO
, P
SAPLLI
, f
MPPLI
)
Added and updated Storage Temperature for 39K200-208EQFP
Changed the I
cc0
spec for 39K165 and 39K200
Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin
Updated
Input and Output Standard Timing Delay Adjustment
table
Removed Self Boot Industrial parts from the offering
Removed Delta39K165Z (1.8V) from the offering
Removed 144-FBGA package offering
Added self-boot Flash Memory endurance and data retention data
Added Family, Package, and Density Migration section
Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs
Changed data sheet status from Preliminary to Final
Added note 7 to DC Characteristics
Updated spec 51-85103 (MG388 package drawing) to rev. *C
Changed the definition of following pins on CY39030 -256FBGA package:
Pin A10: From
IO/Vref7
to
IO/Vref6
Pin B7: From
IO/Vref6
to
V
CC
Added Table to identify Bank Location of Global Clock and Global Control Pins
Removed all “Z” parts (1.8V)
Referenced EEPROM to ATMEL part number
*B
109681
11/16/01
RN
*C
*D
112376
112946
12/21/01
04/04/02
RN
RN
*E
117518
10/04/02
OOR
*F
*G
121063
122543
11/06/02
12/10/02
DSG
RN
*H
128684
08/04/03
OOR
相关PDF资料 |
PDF描述 |
|---|---|
| CY39200V256-200NTI | CPLDs at FPGA Densities |
| CY39200V256-233BBC | CPLDs at FPGA Densities |
| CY39200V256-233BBI | CPLDs at FPGA Densities |
| CY39200V256-233BGC | CPLDs at FPGA Densities |
| CY39200V256-233BGI | CPLDs at FPGA Densities |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39200V256-233MGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V256-233MGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V256-233NTC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-125MGC | 功能描述:IC CPLD 200K GATE 388-BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:Delta 39K™ ISR™ 标准包装:40 系列:ispMACH® 4000C 可编程类型:系统内可编程 最大延迟时间 tpd(1):5.0ns 电压电源 - 内部:1.65 V ~ 1.95 V 逻辑元件/逻辑块数目:32 宏单元数:512 门数:- 输入/输出数:128 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:176-LQFP 供应商设备封装:176-TQFP（24x24） 包装:托盘 |
| CY39200V388-181MGC | 制造商:Cypress Semiconductor 功能描述: |
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