参数资料
型号: CY39200V388-200MGC
厂商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件页数: 63/86页
文件大小: 1235K
代理商: CY39200V388-200MGC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 63 of 86
G16
H1
[19]
H2
[19]
H3
[19]
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
[19]
H15
[19]
H16
[19]
J1
J2
J3
[19]
J4
[19]
J5
[19]
J6
J7
J8
J9
J10
J11
J12
[19]
J13
[19]
J14
[19]
J15
J16
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
IO5
IO0
IO0
IO0
IO5
IO0
IO0
IO0
IO5
IO0
IO0
IO0
IO/V
REF0
IO0
GCLK0
GND
GND
GND
GND
GCLK1
IO5
IO/V
REF5
IO5
IO5
IO5
IO1
IO1
IO1
IO1
IO1
IO1
GND
GND
GND
GND
IO4
IO4
IO4
IO4
IO5
IO5
IO1
V
CCPRG
V
CCIO1
IO/V
REF1
IO1
IO1
GND
GND
GND
GND
IO4
IO/V
REF0
IO0
GCLK0
GND
GND
GND
GND
GCLK1
IO5
IO/V
REF5
IO5
IO5
IO5
IO1
IO1
IO1
IO1
IO1
IO1
GND
GND
GND
GND
IO4
IO4
IO4
IO4
IO5
IO5
IO1
V
CCPRG
V
CCIO1
IO/V
REF1
IO1
IO1
GND
GND
GND
GND
IO4
IO/V
REF0
IO0
GCLK0
GND
GND
GND
GND
GCLK1
IO5
IO/V
REF5
IO5
IO5
IO5
IO1
IO1
IO1
IO1
IO1
IO1
GND
GND
GND
GND
IO4
IO4
IO4
IO4
IO5
IO5
IO1
V
CCPRG
V
CCIO1
IO/V
REF1
IO1
IO1
GND
GND
GND
GND
IO4
Table 13. 256 FBGA Pin Table
(continued)
Pin
CY39030
CY39050
CY39100
相关PDF资料
PDF描述
CY39200V388-200MGI CPLDs at FPGA Densities
CY39200V388-200NC CPLDs at FPGA Densities
CY39200V388-200NI CPLDs at FPGA Densities
CY39200V388-200NTC CPLDs at FPGA Densities
CY39200V388-200NTI CPLDs at FPGA Densities
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