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| 型号： | CY39200V388-233BGI |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件页数： | 18/86页 |
| 文件大小： | 1235K |
| 代理商： | CY39200V388-233BGI |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 18 of 86
Switching Characteristics — Parameter Descriptions
Over the Operating Range
[13]
Parameter
Combinatorial Mode Parameters
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the
horizontal or vertical channel associated with that cluster
t
EA
Global control to output enable
t
ER
Global control to output disable
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel
associated with the cluster the macrocell is in
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated
with the cluster that the macrocell is in to any pin output on those same channels
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest
cluster on the horizontal or vertical channel the pin is associated with
Synchronous Clocking Parameters
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the
cluster that macrocell is in
t
IOS
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
t
IOH
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
t
IOCO
Clock to output of an I/O cell register to the output pin associated with that register
t
SCS
Macrocell clock to macrocell clock through array logic within the same cluster
t
SCS2
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
t
ICS
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the
macrocell is in
t
CHZ
Clock to output disable (high-impedance)
t
CLZ
Clock to output enable (low-impedance)
f
MAX
Maximum frequency with internal feedback—within the same cluster
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or vertical
channel
Product Term Clock
t
MCSPT
Set-up time for macrocell used as input register, from input to product term clock
t
MCHPT
Hold time of macrocell used as an input register
t
MCCOPT
Product term clock to output delay from input pin
t
SCS2PT
Register to register delay through array logic in different clusters on the same channel using a product term clock
Channel Interconnect Parameters
t
CHSW
Adder for a signal to switch from a horizontal to vertical channel and vice-versa
t
CL2CL
Cluster-to-cluster delay adder (through channels and channel PIM)
Miscellaneous Delays
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter
can be added to the t
PD
and t
SCS
parameters for each extra pass through the AND/OR array required by a given
signal path
t
MCCD
Adder for carry chain logic per macrocell
t
IOD
Delay from the input of the output buffer to the I/O pin
t
IOIN
Delay from the I/O pin to the input of the channel buffer
Note:
13. Add t
CHSW
to signals making a horizontal to vertical channel switch or vice-versa.
Description
t
PD
t
PRR
t
PRO
t
PRW
t
MCS
t
MCH
t
MCCO
t
OCS
f
MAX2
t
CPLD
相关PDF资料 |
PDF描述 |
|---|---|
| CY39200V388-233MBC | CPLDs at FPGA Densities |
| CY39200V388-233MBI | CPLDs at FPGA Densities |
| CY39200V388-233NC | CPLDs at FPGA Densities |
| CY39200V388-233NI | CPLDs at FPGA Densities |
| CY39200V388-233NTI | CPLDs at FPGA Densities |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39200V388-233MGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-233MGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-233NTC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-83MGC | 制造商:Cypress Semiconductor 功能描述: |
| CY39200V484-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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