参数资料
型号: CY7C0852AV-133BBI
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 128K X 36 DUAL-PORT SRAM, 4 ns, PBGA172
封装: 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBGA-172
文件页数: 13/36页
文件大小: 956K
代理商: CY7C0852AV-133BBI
CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 20 of 36
Figure 12. Read-to-Write-to-Read (OE Controlled)[37, 38, 39, 40]
Figure 13. Read with Address Counter Advance[39]
Switching Waveforms (continued)
tCYC2
tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
An
An+1
An+2
An+3
An+4
An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ
WRITE
Dn+3
Qn
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
OE
Qn+4
tCD2
Qn+1
tCD2
tSA
tHA
tCH2
tCL2
tCYC2
CLK
ADDRESS
An
COUNTER HOLD
READ WITH COUNTER
tSAD
tHAD
tSCN
tHCN
tSAD
tHAD
tSCN
tHCN
Qx–1
Qx
Qn
Qn+1
Qn+2
Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
ADS
CNTEN
DATAOUT
Notes
37. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only
38. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
39. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
40. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
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