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参数资料
| 型号： | CY7C0853AV-100BBC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| 中文描述： | 256K X 36 DUAL-PORT SRAM, 4.7 ns, PBGA172 |
| 封装： | 15 X 15 MM, 1.25 MM HEIGHT, 1 MM PITCH, FBGA-172 |
| 文件页数： | 5/36页 |
| 文件大小： | 956K |
| 代理商： | CY7C0853AV-100BBC |
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CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 13 of 36
IEEE 1149.1 Serial Boundary Scan (JTAG) [17]
The CY7C0850AV / CY7C0851V / CY7C0851AV / CY7C0852V
/CY7C0852AV / CY7C0853V / CY7C0853AV incorporates an
IEEE 1149.1 serial boundary scan test access port (TAP). The
TAP controller functions in a manner that does not conflict with
the operation of other devices using 1149.1-compliant TAPs. The
TAP operates using JEDEC-standard 3.3 V I/O logic levels. It is
composed of three input connections and one output connection
required by the test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the devices are operating.
An MRST must be performed on the devices after power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
Table 4. Identification Register Definitions
Instruction Field
Value
Description
Revision number (31:28)
0h
Reserved for version number.
Cypress device ID (27:12)
C001h
Defines Cypress part number for the CY7C0851V/0851AV
C002h
Defines Cypress part number for the CY7C0852V/0852AV and
CY7C0853V/0853AV
C092h
Defines Cypress part number for the CY7C0850AV
Cypress JEDEC ID (11:1)
034h
Allows unique identification of the DP family device vendor.
ID register presence (0)
1
Indicates the presence of an ID register.
Table 5. Scan Registers Sizes
Register Name
Bit Size
Instruction
4
Bypass
1
Identification
32
Boundary Scan
n[18]
Table 6. Instruction Identification Codes
Instruction
Code
Description
EXTEST
0000
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
BYPASS
1111
Places the BYR between TDI and TDO.
IDCODE
1011
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
HIGHZ
0111
Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/
CY7C0853AV output drivers to a High-Z state.
CLAMP
0100
Controls boundary to 1/0. Places BYR between TDI and TDO.
SAMPLE/PRELOAD
1000
Captures the input/output ring contents. Places BSR between TDI and TDO.
NBSRST
1100
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
RESERVED
All other codes Other combinations are reserved. Do not use other than the above.
Notes
17. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
18. See details in the device BSDL files.
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相关代理商/技术参数 |
参数描述 |
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| CY7C0853AV-100BBI | 功能描述:静态随机存取存储器 9MB (256Kx36) 3.3v 100MHz Synch 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C0853AV-133BBC | 功能描述:静态随机存取存储器 256Kx36 133MHz 9Mb SYNC DUAL PORT RAM RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C0853AV-133BBI | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 9MBIT 256KX36 4.7NS 172FBGA - Trays |
| CY7C0853V-100BBC | 功能描述:静态随机存取存储器 9MB (256Kx36) 3.3v 100MHz Synch 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C0853V-100BBI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 256K x 36 5ns 172-Pin FBGA 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 256K x 36 4.7ns 172-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:3.3V 256K X 36 SYNC DUALPORT SRAM - Bulk |
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