- 您现在的位置：买卖IC网 > PDF目录295375 > CY7C09179A-7AC SYNC SRAM|32KX9|CMOS|QFP|100PIN|PLASTIC PDF资料下载
参数资料
| 型号： | CY7C09179A-7AC |
| 英文描述： | SYNC SRAM|32KX9|CMOS|QFP|100PIN|PLASTIC |
| 中文描述： | 同步静态存储器| 32KX9 |的CMOS | QFP封装| 100引脚|塑料 |
| 文件页数： | 7/20页 |
| 文件大小： | 301K |
| 代理商： | CY7C09179A-7AC |
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *A
Page 15 of 20
Architecture
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV consist of an array of 4K, 8K, 16K, and 32K
words of 8 and 9 bits each of dual-port RAM cells, I/O and address
lines, and control signals (CE, OE, R/W). These control pins permit
independent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin
is provided on each port. Two interrupt (INT) pins can be utilized for
port-to-port communication. Two semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the device
can function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The device also has an automatic power-
down feature controlled by CE. Each port is provided with its own
output enable control (OE), which allows data to be read from the
device.
Functional Description
Read and Write Operations
When writing data must be set up for a duration of tSD before
the rising edge of R/W in order to guarantee a valid write. A write
operation is controlled by either the R/W pin (see Write Cycle No. 1
waveform) or the CE pin (see Write Cycle No. 2 waveform). Required
inputs for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port tDDD after the data is presented on the other port.
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after OE is
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin and OE must also
be asserted.
Interrupts
The upper two memory locations may be used for message
passing.
The
highest
memory
location
(FFF
for
the
CY7C138AV/9AV, 1FFF for the CY7C144AV/5AV, 3FFF for the
CY7C006AV/16AV, 7FFF for the CY7C007AV/17AV) is the
mailbox for the right port and the second-highest memory lo-
cation
(FFE
for
the
CY7C138AV/9AV,
1FFE
for
the
CY7C144AV/5AV, 3FFE for the CY7C006AV/16AV, 7FFE for
the CY7C007AV/17AV) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is gen-
erated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user de-
fined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it. If an
application does not require message passing, do not connect
the interrupt pin to the processor’s interrupt request input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide on-chip arbitration to resolve simulta-
neous memory location access (contention). If both ports’ CEs are
asserted and an address match occurs within tPS of each other, the
busy logic will determine which port has access. If tPS is violated, one
port will definitely gain permission to the location, but it is not predict-
able which port will get that permission. BUSY will be asserted tBLA
after an address match or tBLC after CE is taken LOW.
Master/Slave
An M/S pin is provided in order to expand the word width by config-
uring the device as either a master or a slave. The BUSY output of
the master is connected to the BUSY input of the slave. This will allow
the device to interface to a master device with no external compo-
nents. Writing to slave devices must be delayed until after the BUSY
input has settled (tBLC or tBLA), otherwise, the slave chip may begin
a write cycle during a contention situation. When tied HIGH, the M/S
pin allows the device to be used as a master and, therefore, the
BUSY line is an output. BUSY can then be used to send the arbitra-
tion outcome to a slave.
Semaphore Operation
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide eight semaphore latches, which
are separate from the dual-port memory locations. Sema-
phores are used to reserve resources that are shared between
the two ports. The state of the semaphore indicates that a
resource is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a zero to a sema-
phore location. The left port then verifies its success in setting
the latch by reading it. After writing to the semaphore, SEM or
OE must be deasserted for tSOP before attempting to read the sema-
phore. The semaphore value will be available tSWRD + tDOE after the
rising edge of the semaphore write. If the left port was successful
(reads a zero), it assumes control of the shared resource, otherwise
(reads a one) it assumes the right port has control and continues to
poll the semaphore. When the right side has relinquished control of
the semaphore (by writing a one), the left side will succeed in gaining
control of the semaphore. If the left side no longer requires the sema-
phore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
remain HIGH during SEM LOW). A0–2 represents the semaphore
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. Howev-
er, if the right port had requested the semaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows sample
semaphore operations.
When reading a semaphore, all data lines output the sema-
phore value. The read value is latched in an output register to
prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the sema-
phore within tSPS of each other, the semaphore will definitely be
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C09179A-9AC | SYNC SRAM|32KX9|CMOS|QFP|100PIN|PLASTIC |
| CY7C09179V | Memory |
| CY7C09179V-9AC | x9 Dual-Port SRAM |
| CY7C09189 | Memory |
| CY7C09189-12AC | x9 Dual-Port SRAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C09179V-12AC | 功能描述:IC SRAM 288KBIT 12NS 100LQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:2,500 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:1K (128 x 8) 速度:100kHz 接口:UNI/O?（单线） 电源电压:1.8 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-MSOP 包装:带卷 (TR) |
| CY7C09179V-12AXC | 功能描述:静态随机存取存储器 3.3V 32Kx9 COM Sync Dual Port 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C09179V-6AXC | 功能描述:静态随机存取存储器 3.3V 32Kx9 COM Sync Dual Port 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C09189-9AC | 功能描述:IC SRAM 576KBIT 67MHZ 100LQFP RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
| CY7C09189V-12AC | 制造商:Cypress Semiconductor 功能描述: |
发布紧急采购，3分钟左右您将得到回复。