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参数资料
型号： CY7C1157V18-333BZXC
厂商： CYPRESS SEMICONDUCTOR CORP
元件分类： SRAM
英文描述： 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
中文描述： 2M X 9 DDR SRAM, 0.45 ns, PBGA165
封装： 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件页数： 3/27页
文件大小： 645K
代理商： CY7C1157V18-333BZXC
CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Document Number: 001-06621 Rev. *D
Page 11 of 27
The write cycle descriptions of CY7C1148V18 follows, [3, 9]
BWS0
BWS1
BWS2
BWS3
K
Comments
LLLL
L – H
–
When the Data portion of a write sequence is active, all four bytes (D[35:0]) are
written into the device.
LLLL
–
L – H When the Data portion of a write sequence is active, all four bytes (D[35:0]) are
written into the device.
L
H
L – H
–
When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
L
H
–
L – H When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
H
L
H
L – H
–
When the Data portion of a write sequence is active, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
–
L – H When the Data portion of a write sequence is active, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
L – H
–
When the Data portion of a write sequence is active, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] remains unaltered.
H
L
H
–
L – H When the Data portion of a Write sequence is active, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] remains unaltered.
H
L
L – H
–
When the Data portion of a write sequence is active, only the byte (D[35:27]) is
written into the device. D[26:0] remains unaltered.
H
L
–
L – H When the Data portion of a write sequence is active, only the byte (D[35:27]) is
written into the device. D[26:0] remains unaltered.
HHHH
L – H
–
No data is written into the device when this portion of a write operation is active.
HHHH
–
L – H No data is written into the device when this portion of a write operation is active.
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相关PDF资料
PDF描述
CY7C1157V18-333BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZXC 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1157V18-375BZXI 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
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