参数资料
型号: CY7C1481V25-133BZC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
中文描述: 2M X 36 CACHE SRAM, 6.5 ns, PBGA165
封装: 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
文件页数: 16/30页
文件大小: 1028K
代理商: CY7C1481V25-133BZC
CY7C1481V25
CY7C1483V25
CY7C1487V25
Document #: 38-05281 Rev. *H
Page 16 of 30
Scan Register Sizes
Register Name
Bit Size (X36)
3
Bit Size (X18)
3
Bit Size (X72)
3
Instruction
Bypass
ID
Boundary Scan Order -165 FBGA
Boundary Scan Order -209 BGA
1
1
32
54
-
1
32
-
112
32
73
-
Identification Codes
Instruction
EXTEST
IDCODE
Code
000
001
Description
Captures IO ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
Boundary Scan Exit Order (2M x 36)
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
165-Ball ID
C1
D1
E1
D2
E2
F1
G1
F2
G2
J1
K1
L1
J2
M1
N1
K2
L2
M2
R1
R2
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-Ball ID
R3
P2
R4
P6
R6
N6
P11
R8
P3
P4
P8
P9
P10
R9
R10
R11
N11
M11
L11
M10
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
165-Ball ID
L10
K11
J11
K10
J10
H11
G11
F11
E11
D10
D11
C11
G10
F10
E10
A10
B10
A9
B9
A8
Bit #
61
62
63
64
65
66
67
68
69
70
71
72
73
165-Ball ID
B8
A7
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
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