参数资料
型号: CY8CLED04D01-56LTXI
厂商: Cypress Semiconductor Corp
文件页数: 13/55页
文件大小: 0K
描述: IC POWERPSOC 4CH 1A 56VQFN
特色产品: PowerPSoC? Embedded Power Controller
标准包装: 260
系列: PowerPSoC® CY8CLED
核心处理器: M8C
芯体尺寸: 8-位
速度: 24MHz
连通性: DALI,DMX512,I²C,IrDA,SPI,UART/USART
外围设备: LED,LVD,POR,PWM,WDT
输入/输出数: 14
程序存储器容量: 16KB(16K x 8)
程序存储器类型: 闪存
RAM 容量: 1K x 8
电压 - 电源 (Vcc/Vdd): 4.75 V ~ 5.25 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 56-VFQFN 裸露焊盘
包装: 托盘
产品目录页面: 698 (CN2011-ZH PDF)
配用: 428-2882-ND - KIT STARTER POWERPSOC LIGHTING
428-2281-ND - KIT EVAL POWERPSOC LIGHTING
428-2270-ND - KIT STARTER DEMO LIGHTING
其它名称: 428-2279
CY8CLED04D01, CY8CLED04D02, CY8CLED04G01
CY8CLED03D01, CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *P
Page 20 of 55
12.2 CY8CLED04G01 56-Pin Part Pinout (without OCD)
The CY8CLED04G01 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and
“FN0”) is capable of Digital I/O.
Table 12-2. CY8CLED04G01 56-Pin Part Pinout (QFN)
Pin
No.
Type
Name
Description
Figure 12-2. CY8CLED04G01 56-Pin PowerPSoC Device
Digital
Rows
Analog
Columns
Power
Peripherals
1
I/O
I
P1[0]
GPIO/I2C SDA (Secondary)/
ISSP SDATA
2
I/O
I
P2[2]
GPIO/Direct Switch Cap connection
3
I/O
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
4
I/O
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
5
I/O
I
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
6
I/O
I
P1[1]
GPIO/I2C SCL (Secondary)/
ISSP SCLK
7
I/O
I
P1[5]
GPIO/I2C SDA (Primary)
8
I/O
I
P1[7]
GPIO/I2C SCL (Primary)
9
VSS
Digital Ground
10
NC
No Connect
11
NC
No Connect
12
NC
No Connect
13
NC
No Connect
14
I
XRES
External Reset
15
VDD
Digital Power Supply
16
VSS
Digital Ground
17
AVSS
Analog Ground
18
AVDD
Analog Power Supply
19
I
CSN2
Current Sense Negative Input 2
20
CSP2
Current Sense Positive Input and
Power Supply - CSA2
21
CSP3
Current Sense Positive Input and
Power Supply - CSA3
22
I
CSN3
Current Sense Negative Input 3
23
SREGCOMP Voltage Regulator Error Amp Comp
24
I
SREGFB
Regulator Voltage Mode Feedback
Node
25
I
SREGCSN
Current Mode Feedback Negative
26
I
SREGCSP
Current Mode Feedback Positive
27
O
SREGSW
Switch Mode Regulator OUT
28
SREGHVIN
Switch Mode Regulator IN
29
GDVDD
Gate Driver Power Supply
Pin
No.
Type
Name
Description
30
GDVSS
Gate Driver Ground
Digital
Rows
Analog
Columns
Power
Peripherals
31
PGND3[3]
Power FET Ground 3
44
GDVDD Gate Driver Power Supply
32
O
GD3
External Low Side Gate Driver 3
45
I/O
FN0[0]
Function I/O
33
DNC[2]
Do Not Connect
46
I/O
FN0[1]
Function I/O
34
PGND2[3]
Power FET Ground 2
47
I/O
FN0[2]
Function I/O
35
O
GD2
External Low Side Gate Driver 2
48
I/O
FN0[3]
Function I/O
36
DNC[2]
Do Not Connect
49
I
CSN0
Current Sense Negative Input 0
37
DNC[2]
Do Not Connect
50
CSP0
Current Sense Positive Input and
Power Supply - CSA0
38
O
GD1
External Low Side Gate Driver 1
51
CSP1
Current Sense Positive Input and
Power Supply - CSA1
39
PGND1[3]
Power FET Ground 1
52
I
CSN1
Current Sense Negative Input 1
40
DNC[2]
Do Not Connect
53
I/O
I
P0[4]
GPIO/Analog Input (Column 1) /
Bandgap Output
41
O
GD0
External Low Side Gate Driver 0
54
VDD
Digital Power Supply
42
PGND0[3]
Power FET Ground 0
55
VSS
Digital Ground
43
GDVSS
Gate Driver Ground
56
I/O
I
P1[4]
GPIO / External Clock Input
Notes
2. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device.
3. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
QFN Top View
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
D
V
S
3
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GD
V
S
GD
V
D
FN
0
[0
]
FN
0
[1
]
FN
0
[2
]
FN
0
[3
]
CS
N
0
C
SP0
CS
P1
CS
N
1
P0
[4
]
VDD
VS
S
P1
[4
]
43
44
45
46
47
48
49
50
51
52
53
54
55
56
PGND0
GD0
DNC
PGND1
GD1
DNC
GD2
PGND2
DNC
GD3
PGND3
GDVSS
GDVDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Exposed
Pad
SREGHV
IN
SRE
G
SW
SRE
G
CSP
SRE
G
C
S
N
SREGFB
SR
EGCOM
P
VD
AS
S
VS
S
AD
D
CN
2
CP
2
CP
3
CS
N
* Connect Exposed Pad to PGNDx
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