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参数资料
| 型号： | CYW2330ZI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 封装： | 0.173 INCH, TSSOP-20 |
| 文件页数： | 1/13页 |
| 文件大小： | 228K |
| 代理商： | CYW2330ZI |
PRELIMINARY
Dual Serial Input PLL with 2.5-GHz and 600-MHz Prescalers
CYW2330
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07239 Rev. **
Revised September 27, 2001
30
Features
Operating voltage: 2.7 V to 5.5 V
PLL1 operating frequency:
— 2.5 GHz with prescaler ratios of 32/33 and 64/65
PLL2 operating frequency:
— 600 MHz with prescaler ratios of 8/9 and 16/17
Lock detect feature
Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
Available in a 24-pin CSP (Chip Scale Package)
Available in a 20-pin MLF
(Mirco Lead Frame Package)
Applications
The Cypress CYW2330 is a dual serial input PLL frequency
synthesizer which includes a 2.5-GHz RF and a 600-MHz IF
dual modulus prescaler to combine the RF and IF mixer fre-
quency sections of wireless communication systems. The syn-
thesizer is designed for cordless/cellular telephone systems,
cable TV tuners, WLANs and other wireless communication
systems. The device operates from 2.7 V and dissipates only
24 mW.
CYW2330 Dual Hi-Lo PLL Block Diagram
Pin Configuration
VCC2
VP2
DOPLL2
GND
FIN2
FIN2#
GND
LE
DATA
CLOCK
20
19
18
17
16
15
14
13
12
11
VCC1
VP1
DOPLL1
GND
FIN1
FIN1#
GND
OSC_IN
GND
FO/LD
1
2
3
4
5
6
7
8
9
10
Binary 6-Bit
Prescaler
Phase
Detector
19-Bit
Pwr-dwn
Swallow Counter
Binary 11-Bit
Programmable Counter
32/33 or
Latch
PLL1
20-Bit Latch
Prescaler
8/9 or
Cntrl 22-Bit
Shift
Reg.
Binary 4-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
19-Bit
Pwr-dwn
Latch
PLL2
15-Bit
Reference Counter
15-Bit
Reference Counter
Phase
Detector
Charge
Pump
fr fp
Monitor
Output
Charge
Pump
Power
Control
Selector
GND (17)
VP2 (19)
GND (9)
GND (14)
GND (4)
GND (7)
VCC1 (1)
VCC2 (20)
FIN1 (5)
FIN1# (6)
OSC_IN (8)
LE (13)
DATA (12)
CLOCK (11)
FIN2 (16)
FIN2# (15)
VP1 (2)
DOPLL1 (3)
FO/LD (10)
DOPLL2 (18)
Latch
Selector
fp1
fr1
fr2
fp2
64/65
16/17
(Top View)
1
2
3
4
5
15
14
13
12
6
7
8
9
10
20
19
18
17
16
11
DoPLL1
GND
Fin1
Fin1#
GND
Fin2
Fin2#
GND
LE
OSC
_
IN
GN
D
Fo
/L
D
CL
O
C
K
DA
TA
Vp
1
Vcc1
Vcc2
Vp
2
DoP
L
2
(Top View)
4
5
6
7
19
18
17
16
10
11
12
24
23
22
15
3
DoPLL1
GND
Fin1
Fin1#
GND
Fin2
Fin2#
GND
LE
GN
D
Fo/
LD
CL
O
C
K
V
cc1
V
cc2
Vp
2
2
1
NC
Vp1
8
9
OSC_IN
NC
14
13
DATA
NC
21
20
NC
DoPLL2
TSSOP
CSP
MLF
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