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参数资料
| 型号： | CYW255OXC |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟及定时 |
| 英文描述： | 255 SERIES, LOW SKEW CLOCK DRIVER, 24 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | LEAD FREE, SSOP-48 |
| 文件页数： | 2/9页 |
| 文件大小： | 129K |
| 代理商： | CYW255OXC |
W255
..........................Document #: 38-07255 Rev. *D Page 2 of 9
Pin Summary
Pin Name
Pins
Pin Description
SEL_DDR
48
Input to configure for DDR-ONLY mode or STANDARD SDRAM
mode.
1 = DDR-ONLY mode.
0 = STANDARD SDRAM mode.
When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin
4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39,
42, 43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode.
When SEL_DDR is pulled LOW or configured for STANDARD SDRAM
output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured
as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42,
43, 44 and 45 will be configured as DDR outputs.
Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM
mode.
SCLK
25
SMBus clock input
SDATA
24
SMBus data input
BUF_IN
13
Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V
input for STANDARD SDRAM mode.
FBOUT
1
Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V.
PWR_DWN#
36
Active LOW input to enable power-down mode; all outputs will be
pulled LOW.
DDR[6:11]T
28, 30, 34, 39, 43, 45
Clock outputs. These outputs provide copies of BUF_IN.
DDR[6:11]C
27, 29, 33, 38, 42, 44
Clock outputs. These outputs provide complementary copies of
BUF_IN.
DDR[0:5]T_SDRAM
[10,0,2,4,6,8]
4, 6, 10, 15, 19, 21
Clock outputs. These outputs provide copies of BUF_IN. Voltage swing
depends on VDD3.3_2.5 power supply.
DDR[0:5]C_SDRAM
[11,1,3,5,7,9]
5, 7, 11, 16, 20, 22
Clock outputs. These outputs provide complementary copies of
BUF_IN when SEL_DDR is active. These outputs provide copies of
BUF_IN when SEL_DDR is inactive. Voltage swing depends on
VDD3.3_2.5 power supply.
VDD3.3_2.5
2, 8, 12, 17, 23
Connect to 2.5V power supply when W255 is configured for
DDR-ONLY mode. Connect to 3.3V power supply, when W255 is
configured for standard SDRAM mode.
VDD2.5
32, 37, 41, 47
2.5V voltage supply
GND
3, 9, 14, 18, 26, 31, 35, 40, 46 Ground
相关PDF资料 |
PDF描述 |
|---|---|
| CYW256OXCT | 256 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| D01-9970121 | SIP1, IC SOCKET |
| D01-9974842 | SIP48, IC SOCKET |
| D03-28-T-A-A-2 | IC SOCKET |
| D03-28-T-B-B-1 | IC SOCKET |
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