参数资料
| 型号： | CYW305OXC |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK W305 SOLANO 56SSOP |
| 标准包装： | 26 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:15 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 56-SSOP |
| 包装： | 管件 |
W305B
...................... Document #: 38-07262 Rev. *B Page 15 of 20
How to Program CPU Output Frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * (N+3)/(M+3)
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 5.
The following table lists the recommended frequency output
ranges for each PLL Gear Constant and its associated Bus
Frequency Ratio so that the maximum AGP and PCI output
frequencies are less than or equal to 83.1 MHz and 41.5 MHz,
respectively.
WD_EN
0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode.
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.
Note. W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery
frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will
not respond to any attempt to change output frequency via the SMBus control bytes. System software
can unlock W305B from its recovery frequency mode by clearing the WD_EN bit.
WD_TO_STATUS
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
WD_TIMER[4:0]
These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the
pre-scaler.
The timer can support a value of 150 ms to 4.8 sec. when the pre-scaler is set to 150 ms. If the pre-scaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.
WD_PRE_SCALER
0 = 150 ms
1 = 2.5 sec
RST_EN_WD
This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
RST_EN_FC
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
Table 6. Register Summary (continued)
Name
Description
Table 7. Recommended CPU Frequency Range for Different PLL Gear Ratio
Gear Constants
Bus Frequency Ratio
(CPU/SDRAM/AGP/PCI)
Recommended Output Frequency Range (CPU/SDRAM/AGP/PCI)
Lower Limits
(N=77, M=48)
Upper Limits
(N=106, M=39)
G1 (32.00494)
66 / 100 / 66 / 33
50.2 / 75.8 / 50.2 / 25.1
83.1 / 124.7 / 83.1 / 41.5
G2 (48.00741)
100 / 100 / 66 / 33
75.3 / 75.3 / 50.2 / 25.1
124.6 / 124.6 / 83.1 / 41.5
G3 (64.00988)
133 / 133 / 66 / 33
or
133 / 100 / 66 / 33
100.4 / 100.4 / 50.2 / 25.1
or
100.4 / 75.3 / 50.2 / 25.1
166.1 / 166.1 / 83.1 / 41.5
or
166.1 / 124.5 / 83.1 / 41.5
G4 (96.01482)
200 / 200 / 66 / 33
150.6 / 150.6 / 50.2 / 25.1
249.2 / 249.2 / 83.1 / 41.5
相关PDF资料 |
PDF描述 |
|---|---|
| DAC5674IPHPG4 | IC DAC 14BIT 400MSPS 48-HTQFP |
| DAC7621EBG4 | IC SNGL 12BIT PARALLEL D/A 20SSO |
| DAC7801KPG4 | IC DUAL 12BIT CMOS DAC 24-DIP |
| DAC8043AESZ | IC DAC 12BIT MULT SRL INP 8SOIC |
| DAC8043GP | IC DAC 12BIT MULTIPLY CMOS 8-DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CYW305OXCT | 功能描述:时钟发生器及支持产品 Legacy-Sys Clk Intel RSolano Chip W305B RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CYW311OXC | 功能描述:时钟发生器及支持产品 Sys Clk VIATM Pro266 DDR Chipset W311 DS RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CYW311OXCT | 功能描述:时钟发生器及支持产品 Sys Clk VIATM Pro266 DDR Chipset W311 DS RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CYW312OXC | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency |
| CYW312OXCT | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:FTG for VIA⑩ K7 Series Chipset with Programmable Output Frequency |
发布紧急采购，3分钟左右您将得到回复。