参数资料
型号: DAC312FR
厂商: Analog Devices Inc
文件页数: 5/14页
文件大小: 0K
描述: IC DAC 12BIT MULT HS 20-CDIP
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 18
设置时间: 250ns
位数: 12
数据接口: 并联
转换器数目: 1
电压电源: 双 ±
功率耗散(最大): 375mW
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 20-CDIP(0.300",7.62mm)
供应商设备封装: 20-CDIP
包装: 管件
输出数目和类型: 2 电流,单极;2 电流,双极
采样率(每秒): *
DAC312
–13–
REV. C
DESCRIPTION OF OPERATION
The DAC312 is divided into two major sections, an 8 segment
generator and a 9-bit master/slave D/A converter. In operation
the device performs as follows (see Simplified Schematic).
The three most significant bits (MSBs) are inputs to a 3-to-8
line decoder. The selected resistor (R5 in the figure) is con-
nected to the master/slave 9-bit D/A converter. All lower order
resistors (R1 through R4) are summed into the IO line, while all
higher order resistors (R6 through R8) are summed into the IO
line. The R5 current supplies 512 steps of current (0 mA to
0.499 mA for a 1 mA reference current) which are also summed
into the IO or IO lines depending on the bits selected. In the fig-
ure, the code selected is: 100 110000000. Therefore, 2 mA (4
×
0.5 mA/segment) +0.375 mA (from master/slave D/A converter)
are summed into IO giving an IO of 2.375 mA. IO has a current
of 1.625 mA with this code. As the three MSB’s are increment-
ed, each successively higher code adds 0.5 mA to IO and sub-
tracts 0.5 mA from IO, with the selected resistor feeding its
current to the master/slave D/A converter; thus each increment
of the 3 MSBs allows the current in the 9-bit D/A converter to
be added to a pedestal consisting of the sum of all lower order
currents from the segment generator. This configuration guar-
antees monotonicity.
Expanded Transfer Characteristic Segment (001 010 011)
Simplified Schematic
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参数描述
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DAC312HR 制造商:PMI 功能描述:
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