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参数资料
| 型号： | DAC5311IDCKR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12 us SETTLING TIME, 8-BIT DAC, PDSO6 |
| 封装： | GREEN, PLASTIC, SC-70, 6 PIN |
| 文件页数： | 25/42页 |
| 文件大小： | 2283K |
| 代理商： | DAC5311IDCKR |
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MICROPROCESSOR INTERFACING
DACx311 to 8051 Interface
SYNC
SCLK
DIN
Microwire
CS
SK
SO
DACx311(1)
NOTE: (1) Additional pins omitted for clarity.
DACx311 to 68HC11 Interface
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
DACx311(1)
NOTE:(1)Additionalpinsomittedforclarity.
80C51/80L51
(1)
P3.3
TXD
RXD
DACx311(1)
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DACx311 to Microwire Interface
www.ti.com ................................................................................................................................................................................................ SBAS442 – AUGUST 2008
Figure 116 shows a serial interface between the
DACx311 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DACx311, while RXD drives
the serial data line of the part. The SYNC signal is
Figure 117. DACx311 to Microwire Interface
derived from a bit programmable pin on the port. In
this case, port line P3.3 is used. When data are to be
transmitted to the DACx311, P3.3 is taken low. The
8051 transmits data only in 8-bit bytes; thus, only
eight falling clock edges occur in the transmit cycle.
Figure 118 shows a serial interface between the
To load data to the DAC, P3.3 remains low after the
DACx311 and the 68HC11 microcontroller. SCK of
first eight bits are transmitted, and a second write
the 68HC11 drives the SCLK of the DACx311, while
cycle is initiated to transmit the second byte of data.
the MOSI output drives the serial data line of the
P3.3 is taken high following the completion of this
DAC. The SYNC signal is derived from a port line
cycle. The 8051 outputs the serial data in a format
(PC7), similar to what was done for the 8051.
which has the LSB first. The DACx311 requires its
data with the MSB as the first bit received. Therefore,
the 8051 transmit routine must take this requirement
into account, and mirror the data as needed.
Figure 118. DACx311 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is a '0' and its CPHA bit is a '1'. This configuration
Figure 116. DACx311 to 80C51/80L51 Interfaces
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is taken
low
(PC7).
Serial
data
from
the
68HC11
are
Figure 117 shows an interface between the DACx311
transmitted in 8-bit bytes with only eight falling clock
and any Microwire-compatible device. Serial data are
edges occurring in the transmit cycle. Data are
shifted out on the falling edge of the serial clock and
transmitted MSB first. In order to load data to the
are clocked into the DACx311 on the rising edge of
DACx311, PC7 is held low after the first eight bits are
the SK signal.
transferred, and a second serial write operation is
performed to the DAC; PC7 is taken high at the end
of this procedure.
Copyright 2008, Texas Instruments Incorporated
31
Product Folder Link(s): DAC5311 DAC6311 DAC7311
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