参数资料
型号: DAC5674IPHP
厂商: Texas Instruments
文件页数: 16/39页
文件大小: 0K
描述: IC DAC 14BIT 400MSPS 48-HTQFP
产品培训模块: Data Converter Basics
标准包装: 250
系列: CommsDAC™
设置时间: 20ns
位数: 14
数据接口: 并联
转换器数目: 1
电压电源: 模拟和数字
功率耗散(最大): 550mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-HTQFP(7x7)
包装: 托盘
输出数目和类型: 2 电流,单极
采样率(每秒): 400M
产品目录页面: 898 (CN2011-ZH PDF)
配用: 296-30860-ND - EVAL MODULE FOR DAC5674
其它名称: 296-15726
296-15726-1
296-15726-1-ND
296-15726-5
296-15726-5-ND
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
23
The amplitudes in Figure 24 are typical values and vary by a few dB across different parts, supply voltages,
and temperatures. Figure 23 and Figure 24 can be used to estimate the non-harmonic clock-related spurious
signals. Take the example for using the DAC5674 in external-clock mode, fDAC = 400 MHz, 4× interpolation,
and IF = 30 MHz. Figure 23 and Figure 24a predict the spurious signals shown in Table 6. The resulting spurs
are at 170 MHz at 38 dBc, 130 MHz at 45 dBc, and 70 MHz at 43 dBc.
Table 6. Predicted Frequency and Amplitude for FDAC 400 MHz, 4y Interpolation
SPURIOUS COMPONENT
SPURIOUS FREQUENCY
AMPLITUDE dBc
IF – fDAC/2
170 MHz
–38
IF + fDAC/4
130 MHz
–45
IF – fDAC/4
70 MHz
–43
IF – 3fDAC/4
>200 MHz
N/A
Figure 25 shows the DAC5674 output spectrum for the preceding example. The amplitudes of the clock-related
spurs agree quite well with the predicted amplitudes in Table 6.
Frequency MHz
80
70
60
50
40
30
20
10
0
10
0
25
50
75
100
125
150
175
200
Amplitude
dBc
IF fDAC/4
IF + fDAC/4
IF 3fDAC/4
IF
Figure 25. DAC Output Spectrum With FDAC = 400 MSPS, 4y Interpolation, IF=30 MHz, External Clock
Digital Inputs
Figure 26 shows a schematic of the equivalent CMOS digital inputs of the DAC5674. The CMOS-compatible
inputs have logic thresholds of IOVDD/2
±20%. The 14-bit digital data input follows the offset positive binary
coding scheme.
D[13:0]
SLEEP
EXTLO
DIV[1:0]
RESET
HP1, HP2
X4
Internal
Digital In
IOVDD (AVDD for SLEEP and EXTLO)
IOGND
Figure 26. CMOS/TTL Digital Equivalent Input
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