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参数资料
| 型号： | DAC7545KUG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 2 us SETTLING TIME, 12-BIT DAC, PDSO20 |
| 封装： | GREEN, PLASTIC, SOIC-20 |
| 文件页数： | 9/14页 |
| 文件大小： | 552K |
| 代理商： | DAC7545KUG4 |
DAC7545
4
SBAS150A
www.ti.com
FIGURE 1. Simplified DAC Circuit of the DAC7545.
RR
2R
R
2R
R
2R
R
FB
2R
OUT 1
AGND
DB0
(LSB)
DB9
DB10
DB11
(MSB)
V
REF
MONOTONICITY
Monotonicity assures that the analog output will increase
or stay the same for increasing digital input codes. The
DAC7545 is ensured monotonic to 12 bits, except the
J grade is specified to be 10-bit monotonic.
POWER-SUPPLY REJECTION
Power-supply rejection is the measure of the sensitivity of the
output (full-scale) to a change in the power-supply voltage.
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of the DAC portion of
the DAC7545. The current from the VREF pin is switched from
OUT 1 to AGND by the FET switch. This circuit architecture
keeps the resistance at the reference pin constant and equal
to RLDR, so the reference can be provided by either a voltage
or current, AC or DC, positive or negative polarity, and have
a voltage range up to
±20V even with V
DD = 5V. The RLDR is
equal to R and is typically 11kW.
The output capacitance of the DAC7545 is code dependent
and varies from a minimum value (70pF) at code 000h to a
maximum (200pF) at code FFFh.
The input buffers are CMOS inverters, designed so that
when the DAC7545 is operated from a 5V supply (VDD), the
logic threshold is TTL-compatible. Being simple CMOS in-
verters, there is a range of operation where the inverters
operate in the linear region and thus draw more supply
current than normal. Minimizing this transition time through
the linear region and insuring that the digital inputs are
operated as close to the rails as possible will minimize the
supply drain current.
DISCUSSION OF
SPECIFICATIONS
RELATIVE ACCURACY
This term (also known as end point linearity) describes the
transfer function of analog output to digital input code.
Relative accuracy describes the deviation from a straight line
after zero and full-scale have been adjusted.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output, for adjacent input code changes. A
differential nonlinearity specification of 1LSB ensures mono-
tonicity.
GAIN ERROR
Gain error is the difference in measure of full-scale output
versus the ideal DAC output; the ideal output for the DAC7545
is –(4095/4096)(VREF). Gain error can be adjusted to zero
using external trims, see the Applications section.
OUTPUT LEAKAGE CURRENT
The current that appears at OUT 1 with the DAC loaded with
all zeros.
MULTIPLYING FEEDTHROUGH ERROR
The AC output error due to capacitive feedthrough from VREF
to OUT 1 with the DAC loaded with all zeros; this test is
performed using a 10kHz sine wave.
OUTPUT CURRENT SETTLING TIME
The time required for the output to settle within
±0.5 LSB
of final value from a change in code of all zeros to all ones,
or all ones to all zeros.
PROPAGATION DELAY
The delay of the internal circuitry is measured as the time
from a digital code change to the point at which the
output reaches 90% of final value.
DIGITAL-TO-ANALOG GLITCH IMPULSE
The area of the glitch energy measured in nanovolt-seconds.
Key contributions to glitch energy are internal circuitry timing
differences
and
charge
injected
from
digital
logic. The measurement is performed with VREF = GND,
an OPA600 as the output op amp, and G1 (phase
compensation) = 0pF.
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