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参数资料
| 型号： | DAC7714U |
| 元件分类： | DAC |
| 英文描述： | QUAD, SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封装： | SO-16 |
| 文件页数： | 5/15页 |
| 文件大小： | 380K |
| 代理商： | DAC7714U |
13
DAC7714
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register inter-
nal to the DAC7714 (see the block diagram on the front of
this data sheet). These two inputs are completely inter-
changeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong DAC.
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
DIGITAL INTERFACE
Figure 4 and Table I provide the basic timing for the
DAC7714. The interface consists of a serial clock (CLK),
serial data (SDI), and a load DAC signal (LOADDACS). In
addition, a chip select (CS) input is available to enable serial
communication when there are multiple serial devices. An
asynchronous reset input (RESET) is provided to simplify
start-up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface (see Figure 4). The first two bits select the DAC
register that will be updated when LOADDACS goes LOW
(see Table II). The next two bits are not used. The last 12 bits
is the DAC code which is provided, most significant bit first.
FIGURE 3. Basic Dual-Supply Operation of the DAC7714.
NOTE: (1) As configured, RESET LOW sets all internal registers to code 800
H (0V).
If RESETSEL is LOW, RESET LOW sets all internal registers to code 000
H (–10V).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
V
SS
RESETSEL
RESET
LOADDACS
NIC
CS
CLK
SDI
GND
Reset DACs(1)
Update Selected Register
Chip Select
Clock
Serial Data In
DAC7714
0.1
F
0.1
F
–10V to +10V
1
F to 10F
+15V
–15V
+
0.1
F
1
F to 10F
+
–10V to +10V
–10.0V
0.1
F
+10.0V
–10V to +10V
+5V
FIGURE 2. Basic Single-Supply Operation of the DAC7714.
NOTE: (1) As configured, RESET LOW sets all internal registers to code 000
H (0V).
If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800
H (5V).
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
V
SS
RESETSEL
RESET
LOADDACS
NIC
CS
CLK
SDI
GND
Reset DACs(1)
Update Selected Register
Chip Select
Clock
Serial Data In
DAC7714
0.1
F
0.1
F
0V to +10.0V
1
F to 10F
+15V
+
0V to +10.0V
+10.000V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DAC7714U | 制造商:Texas Instruments 功能描述:IC DAC 12BIT 89KSPS SOIC-16 制造商:Texas Instruments 功能描述:IC, DAC, 12BIT, 89KSPS, SOIC-16 |
| DAC7714U/1K | 功能描述:数模转换器- DAC Quad Ser In 12-Bit Voltage Output RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC7714U/1KG4 | 功能描述:数模转换器- DAC Quad Ser In 12-Bit Voltage Output RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC7714UB | 功能描述:数模转换器- DAC Quad Ser In 12-Bit Voltage Output RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC7714UB/1K | 功能描述:数模转换器- DAC Quad Ser In 12-Bit Voltage Output RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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