参数资料
型号: DAC8408FSZ-REEL
厂商: Analog Devices Inc
文件页数: 3/16页
文件大小: 0K
描述: IC DAC 8BIT QUAD W/MEMORY 28SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1,000
设置时间: 190ns
位数: 8
数据接口: 并联
转换器数目: 4
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 带卷 (TR)
输出数目和类型: 4 电流,单极;4 电流,双极
采样率(每秒): 5.26M
DAC8408
–11–
REV. A
Figure 7. Quad DAC Bipolar Operation (4-Quadrant Multiplication)
Table II. Bipolar (Offset Binary) Code Table
(Refer to Figure 7)
DAC Data Input
Analog Output
MSB
LSB
(DAC A OR DAC B)
1 1 1 1 1 1 1 1
+VREF
127
128
1 0 0 0 0 0 0 1
+VREF
1
128
1 0 0 0 0 0 0 0
0
0 1 1 1 1 1 1 1
–VREF
1
128
0 0 0 0 0 0 0 1
–VREF
127
128
0 0 0 0 0 0 0 0
–VREF
128
NOTE
1 LSB = (2
–7) (V
REF) =
1
128
(VREF)
APPLICATION HINTS
General Ground Management: AC or transient voltages be-
tween AGND and DGND can appear as noise at the DAC8408’s
analog output. Note that in Figures 5 and 6, IOUT2A/IOUT2B and
IOUT 2C/IOUT 2D are connected to AGND. Therefore, it is rec-
ommended that AGND and DGND be tied together at the
DAC8408 socket. In systems where AGND and DGND are tied
together on the backplane, two diodes (1N914 or equivalent)
should be connected in inverse parallel between AGND and
DGND.
Write Enable Timing: During the period when both DS and
R/W are held low, the DAC latches are transparent and the ana-
log output responds directly to the digital data input. To pre-
vent unwanted variations of the analog output, the R/W should
not go low until the data bus is fully settled (DATA VALID).
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