参数资料
型号: DAC8420FSZ-REEL
厂商: Analog Devices Inc
文件页数: 8/24页
文件大小: 0K
描述: IC DAC 12BIT QUAD SRL LP 16SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1,000
设置时间: 8µs
位数: 12
数据接口: 串行
转换器数目: 4
电压电源: 双 ±
功率耗散(最大): 255mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
输出数目和类型: 4 电压,单极;4 电压,双极
采样率(每秒): 125k
DAC8420
Rev. B | Page 16 of 24
VREFHI INPUT REQUIREMENTS
The DAC8420 utilizes a unique, patented DAC switch driver
circuit that compensates for different supply, reference voltage,
and digital code inputs. This ensures that all DAC ladder switches
are always biased equally, ensuring excellent linearity under all
conditions. Thus, as shown in Table 1, the VREFHI input of the
DAC8420 requires both sourcing and sinking current capabili-
ties from the reference voltage source. Many positive voltage
references are intended as current sources only and offer little
sinking capability. The user should consider references such as
such an application.
POWER-UP SEQUENCE
To prevent a CMOS latch-up condition, power up VDD, VSS,
and GND prior to any reference voltages. The ideal power-up
sequence is GND, VSS, VDD, VREFHI, VREFLO, and digital
inputs. Noncompliance with the power-up sequence over an
extended period can elevate the reference currents and eventually
damage the device. On the other hand, if the noncompliant
power-up sequence condition is as short as a few milliseconds,
the device can resume normal operation without being damaged
once VDD/VSS is powered.
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