参数资料
型号: DAC8551IADGKRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO8
封装: GREEN, PLASTIC, MSOP-8
文件页数: 10/24页
文件大小: 456K
代理商: DAC8551IADGKRG4
www.ti.com
MICROPROCESSOR INTERFACING
DAC8551 to 8051 Interface
Microwire
TM
CS
SK
SO
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8554(1)
DAC8551 to 68HC11 Interface
68HC11
(1)
PC7
SCK
MOSI
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8551(1)
80C51/80L51
(1)
P3.3
TXD
RXD
SYNC
SCLK
D
IN
NOTE:(1)Additionalpinsomittedforclarity.
DAC8554(1)
DAC8551 to Microwire Interface
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
See Figure 50 for a serial interface between the
DAC8551 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8551, while RXD
drives the serial data line of the device. The SYNC
Figure 51. DAC8551 to Microwire Interface
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8551,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
Figure 52 shows a serial interface between the
bytes; thus, only eight falling clock edges occur in
DAC8551 and the 68HC11 microcontroller. SCK of
the transmit cycle. To load data to the DAC, P3.3 is
the 68HC11 drives the SCLK of the DAC8551, while
left LOW after the first eight bits are transmitted, then
the MOSI output drives the serial data line of the
a second write cycle is initiated to transmit the
DAC. The SYNC signal is derived from a port line
second byte of data. P3.3 is taken HIGH following
(PC7), similar to the 8051 diagram.
the completion of the third write cycle. The 8051
outputs the serial data in a format that has the LSB
first. The DAC8551 requires data with the MSB as
the first bit received. The 8051 transmit routine must
therefore take this into account, and mirror the data
as needed.
Figure 52. DAC8551 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
Figure 50. DAC8551 to 80C51/80L51 Interface
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
Figure 51 shows an interface between the DAC8551
transmitted MSB first.) In order to load data to the
and any Microwire-compatible device. Serial data are
DAC8551, PC7 is left LOW after the first eight bits
shifted out on the falling edge of the serial clock and
are transferred, then a second and third serial write
is clocked into the DAC8551 on the rising edge of
operation are performed to the DAC. PC7 is taken
the SK signal.
HIGH at the end of this procedure.
18
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