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参数资料
| 型号： | DC1012A-B |
| 厂商： | Linear Technology |
| 文件页数： | 6/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2497 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1012A Schematic DC1012A Design File |
| 标准包装： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | I²C，串行 |
| 已用 IC / 零件： | LTC2497 |
| 已供物品： | 板 |
| 相关产品： | LTC2497CUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2497IUHF#TRPBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2497IUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN LTC2497CUHF#PBF-ND - IC ADC 16BIT W/PGA 38-QFN |
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LTC2497
2497fa
INPUT DATA FORMAT
The LTC2497 serial input is 8 bits long and is written into
the device in one 8-bit word. SGL, ODD, A2, A1, A0 are
used to select the input channel.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0,
IN– = CH1). The first conversion automatically begins
at power-up using this default input channel. Once the
conversion is complete, a new channel may be written
into the device.
The first three bits of the input word consist of two pre-
amble bits and one enable bit. These three bits are used
to enable the input channel selection. Valid settings for
thesethreebitsare000,100,and101.Othercombinations
should be avoided.
If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
The first input bit (SGL) following the 101 sequence de-
termines if the input selection is differential (SGL = 0) or
single-ended(SGL=1).ForSGL=0,twoadjacentchannels
can be selected to form a differential input. For SGL = 1,
one of 16 channels is selected as the positive input. The
negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
Figure 3a. Timing Diagram for Reading from the LTC2497
applicaTions inForMaTion
SLEEP
DATA OUTPUT
ACK BY
LTC2497
ACK BY
MASTER
ALWAYS LOW
START BY
MASTER
NAK BY
MASTER
LSB
R
MSB
SGN
D15
7
…
8
9
1
2
9
1
2
3
4
5
6
7
8
9
1
7-BIT
ADDRESS
2497 F03a
SCL
SDA
SLEEP
DATA INPUT
ACK BY
LTC2497
ACK BY
LTC2497
NAK BY
LTC2497
START BY
MASTER
SGL ODD
W
0
1
SCL
SDA
EN
A2
A1
A0
7
…
8
9
1
2
9
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
7-BIT ADDRESS
2497 F03b
X
Figure 3b. Timing Diagram for Writing to the LTC2497
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