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参数资料
| 型号： | DC1082A-D |
| 厂商： | Linear Technology |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1403A |
| 软件下载： | QuikEval II System |
| 设计资源： | DC1082A Design File DC1082A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 3M |
| 数据接口： | 串行，SPI? |
| 输入范围： | 0 ~ 2.5 V |
| 已用 IC / 零件： | LTC1403 |
| 已供物品： | 板 |
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LTC1403/LTC1403A
7
1403fb
BLOCK DIAGRAM
PIN FUNCTIONS
AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates
fully differentially with respect to AIN– with a 0V to 2.5V
differential swing and a 0V to VDD common mode swing.
AIN– (Pin 2): Inverting Analog Input. AIN– operates
fully differentially with respect to AIN+ with a –2.5V to 0V
differential swing and a 0V to VDD common mode swing.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND
and to a solid analog ground plane with a 10μF ceramic
capacitor (or 10μF tantalum in parallel with 0.1μF ceramic).
Can be overdriven by an external reference between 2.55V
and VDD.
GND (Pins 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
ow through these pins.
VDD (Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND and to a
solid analog ground plane with a 10μF ceramic capacitor
(or 10μF tantalum in parallel with 0.1μF ceramic). Keep in
mind that internal analog currents and digital output signal
currents ow through this pin. Care should be taken to
place the 0.1μF bypass capacitor as close to Pins 6 and
7 as possible.
SDO (Pin 8): Three-State Serial Data Output. Each of
output data words represents the difference between
AIN+ and AIN– analog inputs at the start of the previous
conversion.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL (≤3V) and 3V CMOS levels. One
or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the analog input signal
and starts the conversion on the rising edge. Responds
to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK
in xed high or xed low state start Nap mode. Four or
more pulses with SCK in xed high or xed low state start
Sleep mode.
1403A BD
–
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC1403A
VREF
10
μF
AIN
–
AIN
+
14-BIT ADC
3V
10
μF
14
14-BIT
LA
TCH
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
5
6
11
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