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| 型号： | DC1190A-B |
| 厂商： | Linear Technology |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2365 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1190A Design Files DC1190A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2365 |
| 已供物品： | 板 |
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LTC2365/LTC2366
5
23656fb
For more information www.linear.com/LTC2365
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When this pin, AIN, is taken below GND or above VDD, it will be
clamped by internal diodes. These products can handle input currents
greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and
fSCK = fSCK(MAX) unless otherwise specified.
Note 5: Integral linearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Linearity, offset and gain specifications apply for a single-ended
AIN input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 8: Guaranteed by characterization. All input signals are specified with
tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specifications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: Minimum fSCK at which specifications are guaranteed.
Note 11: The time required for the output to cross the VIH or VIL voltage.
Note 12: Guaranteed by design, not subject to test.
Note 13: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
SYMBOL
PARAMETER
CONDITIONS
LTC2365
LTC2366
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
fSMPL(MAX)
Maximum Sampling Frequency
(Notes 8, 9)
l
1
3
MHz
fSCK
Shift Clock Frequency
(Notes 8, 9, 10)
l
0.5
16
0.5
48
MHz
tSCK
Shift Clock Period
l
62.5
2000
20.8
2000
ns
tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV
l
1000
333
ns
tACQ
Acquisition Time
l
181.5
56
ns
tCONV
Conversion Time
l
818.5
277
ns
tQUIET
SDO Hi-Z State to CS
↓
(Notes 8, 9)
l
4
ns
t1
Minimum Positive or Negative CS Pulse Width (Notes 8)
l
4
ns
t2
SCK
↓ Setup Time After CS↓
(Notes 8)
l
6
2000
6
2000
ns
t3
SDO Enabled Time After CS
↓
(Notes 9, 11, 12)
l
4
ns
t4
SDO Data Valid Access Time After SCK
↓
(Notes 8, 9, 11)
l
15
ns
t5
SCK LOW Time
l
40%
tSCK
t6
SCK HIGH Time
l
40%
tSCK
t7
SDO Data Valid Hold Time After SCK
↓
(Notes 8, 9, 11)
l
5
ns
t8
SDO into Hi-Z State Time After SCK
↓
(Notes 9, 12)
l
5
30
5
14
ns
t9
SDO into Hi-Z State Time After CS
↑
(Notes 9, 12)
l
4.2
ns
tPOWER-UP
Power-Up Time from Sleep Mode
See Sleep Mode section
l
1000
333
ns
tiMing characteristics The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
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