参数资料
型号: DC1496A-A
厂商: Linear Technology
文件页数: 7/16页
文件大小: 0K
描述: BOARD EVAL LTC2941
软件下载: QuikEval System
设计资源: DC1496A Design Files
DC1496A Schematic
标准包装: 1
系列: QuikEval™
主要目的: 电源管理,电池监控器
嵌入式:
已用 IC / 零件: LTC2941
主要属性: I²C、SMBus 接口
次要属性: LED 状态指示器
已供物品: 板,线缆
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LTC2941
APPLICATIONS INFORMATION
I 2 C/SMBus Interface
The LTC2941 communicates with a bus master using a
2-wire interface compatible with I 2 C and SMBus. The 7-bit
hard-coded I 2 C address of LTC2941 is 1100100 .
The LTC2941 is a slave-only device. Therefore the serial
clock line (SCL) is input only while the data line (SDA) is
bidirectional. For more details refer to the I 2 C Protocol
section.
Status Register (A)
Table 2 shows the details of the status register (address
00h):
Table 2. Status Register A (Read Only)
BIT NAME OPERATION DEFAULT
A[7] Chip Identification 1: LTC2941 1
0: LTC2942
A[6] Reserved Not Used. 0
Internal Registers
The LTC2941 integrates current through a sense resistor
and stores a 16-bit result, accumulated charge, as two
bytes in registers C and D. Two byte high and low limits
programmed in registers E, F, G and H are continuously
compared against the accumulated charge. If either limit is
exceeded, a corresponding flag is set in the status register
bits A[2] or A[3]. If the alert mode is enabled, the AL /CC
pin pulls low.
The internal eight registers are organized as shown in
Table 1:
Table 1. Register Map
ADDRESS NAME REGISTER DESCRIPTION R/W DEFAULT
A[5] Accumulated Charge
Overflow/Underflow
A[4] Reserved
A[3] Charge Alert High
A[2] Charge Alert Low
A[1] V BAT Alert
A[0] Undervoltage
Lockout Alert
Indicates that the value of the
accumulated charge hit either
top or bottom.
Not used.
Indicates that the accumulated
charge value exceeded the
charge threshold high limit.
Indicates that the accumulated
charge value dropped below
the charge threshold low limit.
Indicates that the battery
voltage (at SENSE – ) dropped
below selected V BAT threshold.
Indicates recovery from
undervoltage. If equal to 1,
a UVLO has occurred and
the content of registers is
uncertain.
0
0
0
0
0
X
00h
01h
02h
03h
04h
A
B
C
D
E
Status
Control
Accumulated Charge MSB
Accumulated Charge LSB
Charge Threshold High MSB
R
R/W
R/W
R/W
R/W
See Below
3Ch
7Fh
FFh
FFh
The AL /CC pin can be configured to pull low whenever any
status register bit is set (except for bit A[7] and A[0]), us-
ing control register bits B[2] and B[1]. All status register
bits except A[7] are cleared after being read by the host
if the conditions which set these bits have been removed.
05h F
06h G
07h H
R = Read, W = Write
Charge Threshold High LSB
Charge Threshold Low MSB
Charge Threshold Low LSB
R/W
R/W
R/W
FFh
00h
00h
As soon as one of the measured quantities exceeds the
programmed limits, the corresponding bit A[3], A[2] or
A[1] in the status register is set.
2941fa
7
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