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参数资料
| 型号： | DC790A |
| 厂商： | Linear Technology |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2439-1 |
| 软件下载： | QuikEval System |
| 设计资源： | DC790A Design File DC790A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 6.8 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2439-1 |
| 已供物品： | 板 |
| 相关产品： | LTC2439-1CGN#PBF-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP LTC2439-1IGN#PBF-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP LTC2439-1CGN#TRPBF-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP LTC2439-1IGN#TRPBF-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP LTC2439-1CGN-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP LTC2439-1IGN-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP LTC2439-1IGN#TR-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP LTC2439-1CGN#TR-ND - IC ADC 16BIT 16CH MCRPWR 28SSOP |
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LTC2439-1
21
24391fa
Figure 12), a first order passive network with a time
constant
τ = (RS + RSW) CEQ. The converter is able to
sample the input signal with better than 1LSB accuracy if
the sampling period is at least 11 times greater than the
input circuit time constant
τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (FO = LOW), the
LTC2439-1’s front-end switched-capacitor network is
clocked at 69900Hz corresponding to a 14.3
s sampling
period. Thus, for settling errors of less than 1LSB, the
driving source impedance should be chosen such that
τ ≤ 14.3s/11 = 1.3s. When an external oscillator of
APPLICATIO S I FOR ATIO
WU
UU
frequency fEOSC is used, the sampling period is 2/fEOSC
and, for a settling error of less than 1LSB,
τ ≤ 0.18/fEOSC.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 12 shows the
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
VREF+
VIN+
VCC
RSW (TYP)
20k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
20k
CEQ
18pF
(TYP)
RSW (TYP)
20k
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
24391 F11
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 69900Hz INTERNAL OSCILLATOR (FO = LOW)
fSW = 0.5 fEOSC EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
20k
Figure 12. LTC2439-1 Equivalent Analog Input Circuit
IIN
VV
V
R
IIN
VV
V
R
I REF
VV
V
R
V
VR
I REF
VV
V
R
V
VR
where
AVG
IN
INCM
REFCM
EQ
AVG
IN
INCM
REFCM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
+
+
() = +
() = +
() = +
() = +
+
05
15
05
15
05
2
.
::
./
V
REF
V
REF
VIN
IN
V
IN
R
M
INTERNAL OSCILLATOR
Hz
Hz Notch F
LOW
R
f
EXTERNAL OSCILLATOR
REF
REFCM
IN
INCM
EQ
O
EQ
EOSC
=
=
+
=
=
==
()
=
()
+
+
+
+
2
397
50
60
0 555 1012
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