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参数资料
| 型号： | DC812A |
| 厂商： | Linear Technology |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | BOARD DAC LTC2606 |
| 软件下载： | QuikEval System |
| 设计资源： | DC812A Design File DC812A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| DAC 的数量： | 1 |
| 位数： | 16 |
| 数据接口： | I²C |
| 设置时间： | 10µs |
| DAC 型： | 电压 |
| 工作温度： | 0°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2606 |
| 相关产品： | LTC2606CDD-1#PBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN LTC2606IDD-1#PBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN LTC2606IDD#PBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN LTC2606CDD#PBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN LTC2606IDD#TRPBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN LTC2606IDD-1#TRPBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN LTC2606CDD-1#TRPBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN LTC2606CDD#TRPBF-ND - IC DAC 16BIT I2C V-OUT 10-DFN |
LTC2606/LTC2616/LTC2626
16
26061626fb
OPERATION
The DAC is powered up when LDAC is taken low, inde-
pendent of any activity on the I2C bus.
If LDAC is low at the falling edge of the 9th clock of the
3rd byte of data, it inhibits any software power-down
command that was specied in the input word.
Voltage Output
The rail-to-rail amplier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at
3V).
Load regulation is a measure of the amplier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The ampliers’ DC output
impedance is 0.050Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω 1mA = 25mV. See the graph Headroom at Rails
vs Output Current in the Typical Performance Charac-
teristics section.
The amplier is stable driving capacitive loads of up to
1000pF.
Board Layout
The excellent load regulation performance is achieved in
part by keeping “signal” and “power” grounds separated
internally and by reducing shared internal resistance.
The GND pin functions both as the node to which the refer-
ence and output voltages are referred and as a return path
for power currents in the device. Because of this, careful
thought should be given to the grounding scheme and
board layout in order to ensure rated performance.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shield it from noise. Analog ground should be a continuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin of the part should be connected to analog
ground. Resistance from the GND pin to system star
ground should be as low as possible. Resistance here
will add directly to the effective DC output impedance
of the device (typically 0.050Ω). Note that the LTC2606/
LTC2616/LTC2626 are no more susceptible to these ef-
fects than other parts of their type; on the contrary, they
allow layout-based performance improvements to shine
rather than limiting attainable performance with excessive
internal resistance.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure 5b. Similarly, limiting can occur near full-scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 5c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are dened and tested over the region
of the DAC transfer function where no output limiting
can occur.
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