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参数资料
| 型号： | DC873A |
| 厂商： | Linear Technology |
| 文件页数： | 15/16页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1867L |
| 软件下载： | QuikEval System |
| 设计资源： | DC873A Schematic DC873A Design Files |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 175k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC1867L |
| 已供物品： | 板 |
| 相关产品： | LTC1867ACGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867LIGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867IGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867LACGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867CGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867IGN#TRPBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867AIGN#PBF-ND - IC ADC 16BIT 8CH 200KSPS 16SSOP LTC1867LAIGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867LCGN#PBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP LTC1867LACGN#TRPBF-ND - IC ADC 16BIT 8CH 175KSPS 16SSOP 更多... |
LTC1863/LTC1867
8
18637fa
TIMING DIAGRAMS
t5 (SDI Setup Time Before SCK↑),
t6 (SDI Hold Time After SCK↑)
50%
t3
0.4V
t7 (SLEEP Mode Wake-Up Time)
t7
SCK
CS/CONV
t8 (BUS Relinquish Time)
t8
CS/CONV
SDO
2.4V
t4 (SDO Valid After CONV↓)
t4
CS/CONV
SDO
2.4V
0.4V
t6
2.4V
0.4V
t5
SCK
SDI
2.4V
0.4V
2.4V
0.4V
SDO
1867 TD
SLEEP BIT (SLP = 0)
READ-IN
10%
90%
Hi-Z
t1 (For Short Pulse Mode)
t2 (SDO Valid Before SCK↑),
t3 (SDO Valid Hold Time After SCK↓)
t1
CS/CONV
t2
SCK
50%
Overview
The LTC1863/LTC1867 are complete, low power multi-
plexed ADCs. They consist of a 12-/16-bit, 200ksps capaci-
tive successive approximation A/D converter, a precision
internal reference, a congurable 8-channel analog input
multiplexer (MUX) and a serial port for data transfer.
Conversions are started by a rising edge on the CS/CONV
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, the ADCs receive an input
word for channel selection and output the conversion
result, and the analog input is acquired in preparation for
the next conversion. In the acquire phase, a minimum time
of 1.5μs will provide enough time for the sample-and-hold
capacitors to acquire the analog signal.
During the conversion, the internal differential 16-bit
capacitive DAC output is sequenced by the SAR from
the most signicant bit (MSB) to the least signicant bit
(LSB). The input is sucessively compared with the binary
weighted charges supplied by the differential capacitive
DAC. Bit decisions are made by a low-power, differential
comparator. At the end of a conversion, the DAC output
balances the analog input. The SAR contents (a 12-/16-bit
data word) that represent the analog input are loaded into
the 12-/16-bit output latches.
APPLICATIONS INFORMATION
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| DC887A | 功能描述:BOARD SAR ADC LTC1408 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:QuikEval-II™ 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
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