参数资料
型号: DEMO56F8014-EE
厂商: Freescale Semiconductor
文件页数: 93/124页
文件大小: 0K
描述: BOARD DEMO FOR 56F8014
标准包装: 1
类型: MCU
适用于相关产品: 56F8014
所含物品: 板,线缆,CD,电源
配用: APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
相关产品: MC56F8014VFAE-ND - IC DIGITAL SIGNAL CTRLR 32-LQFP
56F8014 Technical Data, Rev. 11
70
Freescale Semiconductor
The lower four bits of the GPIO A register can function as GPIO, PWM, or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOA_PEREN. If GPIOA[3:0] are
programmed to operate as peripheral outputs, then the choice between PWM and additional clock outputs
is done here in the CLKOUT. The default state is for the peripheral function of GPIOA[3:0] to be
programmed as PWM. This can be changed by altering PWM3 through PWM0.
Figure 6-8 CLKO Select Register (SIM_CLKOUT)
6.3.7.1
Reserved—Bits 15–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.7.2
PWM3—Bit 9
0 = Peripheral output function of GPIOA[3] is defined to be PWM3
1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
6.3.7.3
PWM2—Bit 8
0 = Peripheral output function of GPIOA[2] is defined to be PWM2
1 = Peripheral output function of GPIOA[2] is defined to be the system clock
6.3.7.4
PWM1—Bit 7
0 = Peripheral output function of GPIOA[1] is defined to be PWM1
1 = Peripheral output function of GPIOA[1] is defined to be two times the rate of the system clock
6.3.7.5
PWM0—Bit 6
0 = Peripheral output function of GPIOA[0] is defined to be PWM0
1 = Peripheral output function of GPIOA[0] is defined to be three times the rate of the system clock
6.3.7.6
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is 0
6.3.7.7
Clockout Select (CLKOSEL)—Bits 4–0
Selects clock to be muxed out on the CLKO pin.
00000 = Reserved for factory test—Continuous system clock
01001 = Reserved for factory test—OCCS MSTR OSC clock
01011 = Reserved for factory test—ADC clock
01100 = Reserved for factory test—JTAG TCLK
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWM
3
PWM
2
PWM1PWM0
CLK
DIS
CLKOSEL
Write
RESET
0
000
0
1
0
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