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参数资料
型号： DG2301DL
厂商： Vishay Intertechnology,Inc.
英文描述： High-Speed, Low rON, SPST Analog Switch
中文描述： 高速，低RON，SPST模拟开关
文件页数： 2/5页
文件大小： 33K
代理商： DG2301DL
DG2301
Vishay Siliconix
New Product
www.vishay.com
2
Document Number: 72049
S-03420—Rev. A, 03-Mar-03
ABSOLUTE MAXIMUM RATINGS
Reference to GND
V+
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OE, A, B
a
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous Current (Any terminal)
Peak Current
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(Pulsed at 1 ms, 10% duty cycle)
Storage Temperature (D Suffix)
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.3 to +6 V
-0.3 to (V+ + 0.3 V)
50 mA
200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . .
-65 to 150
°
C
Power Dissipation (Packages)
b
6-Pin SC70
c
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
250 mW
Notes:
a.
Signals on A, or B or OE exceeding V+ will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
All leads welded or soldered to PC Board.
Derate 3.1 mW/ C above 70 C
b.
c.
SPECIFICATIONS (V+ = 5.0 V)
Test Conditions
Otherwise Unless Specified
Limits
-40 to 85 C
Parameter
Symbol
V+ = 4.0 V to 5.5 V, V
OE
= 0.8 or 2.0 V
e
Temp
a
Min
b
Typ
c
Max
b
Unit
DC Characteristics
V+ = 4.5 V, V
A
= 0 V, I
B
= 64 mA
Full
7
On Resistance
On-Resistance
r
ON
V+ = 4.5 V, V
A
= 0 V, I
B
= 30 mA
Full
7
V+ = 4.5 V, V
A
= 2.4 V, I
B
= 15 mA
Full
15
V+ = 4.0 V, V
A
= 2.4 V, I
B
= 15 mA
Full
20
Switch Off Leakage Current
I
(off)
V+ = 5.5 V, V
A
= 1 V/4.5 V, V
B
= 4.5 V/1 V
Full
-10
10
A
Switchl-On Leakage Current
I
(on)
V+ = 5.5 V, V
A
= V
B
= 1 V/4.5 V
Full
-10
10
Input High Voltage
V
IH
Full
2.0
V
Input Low Voltage
V
IL
Full
0.8
Input Current
I
IL
or I
IH
V
OE
= 0 or V+
Full
-1
1
A
Dynamic Characteristics
Prop Delay Bus to Bus
Prop Delay Bus-to-Bus
f
t
PHL
V
LD
= Open (Figure 1 and 2)
Full
1
t
PLH
Full
1
t
PZL
V
LD
= 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
3.9
Output Enable Time
d
V
LD
= 7 V, V+ = 4.0 V (Figure 1 and 2)
Full
4.5
t
PZH
V
LD
= Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
3.7
ns
V
LD
= Open, V+ = 4.0 V (Figure 1 and 2)
Full
4.5
t
PLZ
V
LD
= 7 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
4.0
Output Disable Time
d
V
LD
= 7 V, V+ = 4.0 V (Figure 1 and 2)
Full
4.2
t
PHZ
V
LD
= Open, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
1.0
V
LD
= Open, V+ = 4.0 V (Figure 1 and 2)
Full
1.0
Input Capacitance
C
in
Room
3.5
Channel-Off Capacitance
d
C
(off)
= 0 or V+ f = 1 MHz
V
OE
= 0 or V+, f = 1 MHz
Room
5
pF
Channel-On Capacitance
d
C
ON
Room
11
Power Supply
Power Supply Range
V+
4.0
5.5
V
Power Supply Current
I+
V
OE
= 0 or V+
0.01
1.0
A
Notes:
a.
b.
c.
d.
e.
f.
Room = 25
°
C, Full = as determined by the operating suffix.
The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
Typical values are for design aid only, not guaranteed nor subject to production testing.
Guarantee by design, nor subjected to production test.
V
= input voltage to perform proper function.
Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and
the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
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相关代理商/技术参数
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