参数资料
| 型号： | DG2303DL-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 3/6页 |
| 文件大小： | 0K |
| 描述： | IC SW ONE HS SPST 1.8/5V SC70-5 |
| 标准包装： | 3,000 |
| 功能： | 开关 |
| 电路： | 1 x SPST |
| 导通状态电阻： | 15 欧姆 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 1.65 V ~ 5.5 V |
| 电流 - 电源： | 1µA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP（5 引线），SC-88A，SOT-353 |
| 供应商设备封装： | SC-70-5 |
| 包装： | 带卷 (TR) |
Document Number: 72073
S-70852-Rev. B, 30-Apr-07
www.vishay.com
3
Vishay Siliconix
DG2303
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the
on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 1.65 V to 5.5 V, VIN = VIH or VIL
e
Tempa
Limits
- 40 to 85 °C
Unit
Minb
Typc
Maxb
Dynamic Characteristics
Prop Delay Bus-to-Busf
tPHL, tPLH
VLD = Open, V = 1.65 V to 1.95 V, (Figure 1 and 2)
Full
5
ns
VLD = Open, V = 2.3 V to 2.7 V, (Figure 1 and 2)
Full
2
VLD = Open, V = 3.0 V to 3.6 V, (Figure 1 and 2)
Full
1
VLD = Open, V = 4.5 V to 5.5 V, (Figure 1 and 2)
Full
1
Output Enable Timed
tPZL
VLD = 2 x V+, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
4.2
VLD = 2 x V+, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
3.3
VLD = 2 x V+, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
2.6
VLD = 2 x V+, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
1.8
tPZH
VLD = 0 V, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
4.4
VLD = 0 V, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
3.3
VLD = 0 V, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
2.7
VLD = 0 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
2.0
Output Disable Timed
tPLZ
VLD = 2 x V+, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
14.3
VLD = 2 x V+, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
10.5
VLD = 2 x V+, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
8.6
VLD = 2 x V+, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
7.4
tPHZ
VLD = 0 V, V+ = 1.65 V to 1.95 V (Figure 1 and 2)
Full
10.7
VLD = 0 V, V+ = 2.3 V to 2.7 V (Figure 1 and 2)
Full
9.6
VLD = 0 V, V+ = 3.0 V to 3.6 V (Figure 1 and 2)
Full
8.7
VLD = 0 V, V+ = 4.5 V to 5.5 V (Figure 1 and 2)
Full
7.5
Charge Injectiond
QINJ
CL = 1 nF, VGEN = 0 V, RGEN = 0 Ω, (Figure 3)
Room
0.5
pC
Off Isolationd
OIRR
RL = 50 Ω, CL = 5 pF, f = 10 MHz
Room
- 50
dB
Insertion Lossd
Loss
RL = 50 Ω
Room
> 200
MHz
Input Capacitanced
Cin
Room
4
pF
Channel-Off Capacitanced
C(off)
VOE = 0 or V+, f = 1 MHz
Room
9
Channel-On Capacitanced
CON
Room
20
Power Supply
Power Supply Range
V+
1.65
5.5
V
Power Supply Current
I+
VOE = 0 or V+
1.0
A
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