DG2535/DG2536

Vishay Siliconix

New Product

Document Number: 72939

S-41967—Rev. B, 01-Nov-04

www.vishay.com

5

TEST CIRCUITS

FIGURE 2.

Break-Before-Make Interval

C

L

= 1 nF

R

gen

V

OUT

COM

V

IN

= 0

V+

IN

GND

V+

V+

+

NC or NO

FIGURE 3.

Charge Injection

C

L

(includes fixture and stray capacitance)

NC

V

NO

NO

V

NC

0 V

Logic

Input

Switch

Output

V

O

V

NC

= V

NO

90%

t

D

IN

COM

V+

GND

V+

C

L

35 pF

V

O

R

L

300

V

INL

V

INH

t

r

t

f

5 ns

5 ns

t

D

Off

On

On

IN

V

OUT

V

OUT

Q = V

OUT

x C

L

IN depends on switch configuration: input polarity

determined by sense of switch.

FIGURE 4.

Off-Isolation

FIGURE 5.

Channel Off/On Capacitance

NC or NO

IN

COM

GND

0 V, 2.4 V

Meter

HP4192A

Impedance

Analyzer

orf = 1 MHz

10 nF

V+

V+

IN

GND

NC or NO

0V, 2.4 V

10 nF

COM

Off Isolation

20 log

V

COM

V

NO NC

R

L

Analyzer

V+

V+

COM

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and

Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see