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参数资料
| 型号： | DG413FEUE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH QUAD SPST 16TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 功能： | 开关 |
| 电路： | 4 x SPST - NC/NO |
| 导通状态电阻： | 85 欧姆 |
| 电压电源： | 单/双电源 |
| 电压 - 电源，单路/双路(±)： | 9 V ~ 36 V，±4.5 V ~ 20 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
Detailed Description
The DG411F/DG412F/DG413F are fault-protected
CMOS analog switches with unique operation and
construction. These switches differ considerably from
traditional fault-protection switches, with several advan-
tages. First, they are constructed with two parallel
FETs, allowing very low on-resistance when the switch
is on. Second, they allow signals on the NO_ or NC_
pins that are within, or slightly beyond, the supply rails
to be passed through the switch to the COM_ terminal
(or vice versa), allowing true rail-to-rail signal operation.
Third, the DG411F/DG412F/DG413F have the same
fault-protection performance on any of the NO_, NC_,
or COM_ switch inputs. Operation is identical for both
fault polarities. The fault protection extends to ±36V
from GND with
±15V supplies.
During a fault condition, the particular overvoltage input
(COM_, NO_, NC_) pin becomes high impedance
regardless of the switch state or load resistance. When
power is removed, the fault protection is still in effect. In
this case, the COM_, NO_, or NC_ terminals are a virtu-
al open circuit. The fault can be up to ±40V with power
off. The switches turn off when V+ is not powered,
regardless of V-.
Pin Compatibility
These switches have identical pinouts to common non-
fault-protected CMOS switches. They allow for carefree
direct replacement in existing printed circuit boards
since the NO_, NC_, and COM_ pins of each switch are
fault protected.
Internal Construction
Internal construction is shown in Figure 1, with the ana-
log signal paths shown in bold. A single NO switch is
shown. The NC configuration is identical except the
logic-level translator becomes an inverter. The analog
switch is formed by the parallel combination of N-chan-
nel FET (N1) and P-channel FET (P1), which are driven
on and off simultaneously according to the input fault
condition and the logic-level state.
Normal Operation
Two comparators continuously compare the voltage on
the COM_, NO_, and NC_ pins with V+ and V-. When
the signal on COM_, NO_, or NC_ is between V+ and
V-, the switch acts normally, with FETs N1 and P1 turn-
ing on and off in response to IN_ signals. The parallel
combination of N1 and P1 forms a low-value resistor
between NO_ (or NC_) and COM_ so that signals pass
equally well in either direction.
Positive Fault Condition
When the signal on NO_ (or NC_) and COM_ exceeds
V+ by about 50mV, the high-fault comparator output is
high, turning off FETs N1 and P1. This makes the NO_
(or NC_) and COM_ pins high impedance regardless of
DG411F/DG412F/DG413F
Quad, Rail-to-Rail, Fault-Protected,
SPST Analog Switches
_______________________________________________________________________________________
9
PIN
DG411F
DG412F
DG413F
NAME
FUNCTION
1, 16, 9, 8
IN1, IN2, IN3, IN4
Logic Control Digital Inputs
2, 15, 10, 7
COM1, COM2, COM3,
COM4
Analog Switch Common Terminals
3, 14, 11, 6
——
NC1, NC2, NC3, NC4
Analog Switch Normally Closed Terminals
—
3, 14, 11, 6
—
NO1, NO2, NO3, NO4
Analog Switch Normally Open Terminals
——
3, 6
NO1, NO4
Analog Switch Normally Open Terminals
——
14, 11
NC2, NC3
Analog Switch Normally Closed Terminals
44
4
V-
Negative-Supply Voltage Input. Connect to GND for single-
supply operation. Bypass with a 0.1F capacitor to GND.
5
GND
Ground. Connect to digital ground.
12
N.C.
No Connection. Not internally connected.
13
V+
Positive-Supply Voltage Input. Bypass with a 0.1F capacitor
to GND.
Pin Description
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相关代理商/技术参数 |
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| DG413HS | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Precision Monolithic Quad SPST CMOS Analog Switches |
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