参数资料
型号: DG884AM883
厂商: Vishay Intertechnology,Inc.
英文描述: 8 x 4 Wideband Video Crosspoint Array
中文描述: 8 × 4交叉点阵列宽带视频
文件页数: 7/14页
文件大小: 166K
代理商: DG884AM883
DG884
Vishay Siliconix
Document Number: 70071
S-52433—Rev. G, 20-Dec-04
www.vishay.com
7
TIMING DIAGRAMS
FIGURE 1.
Input Timing Requirements
t
SW
t
AW
Presetting Device A
CS for
CS for
B
0
B
1
Address
A
0
A
3
WR
SALVO
RS
I/O
Select Output 1
Presetting Device B
Don’t Care
Don’t Care
Select Output 2
Output N
Select Input
Select Input
Input
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
t
WA
t
WA
t
AW
t
WA
t
WP
t
SP
t
RS
t
CW
t
CA
t
IA
t
WS
t
AW
t
WC
t
SP
t
SW
t
CW
t
WS
Input
FIGURE 2.
Output Timing Requirements
t
AO
t
AO
CS for
Device A
CS for
Device B
Interrogating Device A
Address
B
0
B
1
Address
A
0
A
3
WR
SALVO
RS
I/O
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
t
IO
Select Current
Event Latch
Interrogating Device B
Output
t
C
O
t
AO
Latch N
t
CA
Out N
t
C
O
t
C
A
t
AO
t
IA
Address Output 1
Address Output
PARAMETER DEFINITIONS
Symbol
Parameter
Description
T
AW
T
WA
T
WP
T
CW
T
WC
T
SP
T
WS
T
SW
T
IA
T
RS
T
IO
T
AO
T
CO
T
CA
Address to Write
Minimum time address must be valid before WR goes high
Write to Address
Minimum time address must remain valid after WR pulse goes high
WR Pulse
Minimum time of WR pulse width to write address into Next Event latches
Chip Select to WR
Minimum time chip select must be valid before a WR pulse
WR to Chip Select
Minimum time chip select must remain valid after WR pulse
SALVO Pulse
Minimum time of SALVO pulse width
WR to SALVO
Minimum time from WR pulse to SALVO to load new address
SALVO to WR
Minimum time from SALVO pulse to WR to load current address
I/O to Address In
Minimum time I/O must be valid before address applied
RS to SALVO
Minimum time RS must be valid before SALVO pulse
I/O to Output
Minimum time I/O must be valid before address output valid
Address to Output
Minimum time address B
X
must be valid until address A
X
output valid
Minimum time CS must be valid until A
X
output is valid
Minimum time CS must be valid before address applied if I/O is high
CS to Output
CS to Address In
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