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参数资料
| 型号： | DG894 |
| 厂商： | Vishay Intertechnology,Inc. |
| 英文描述： | Component Video Selector(用于视频信号转换的视频选择器) |
| 中文描述： | 分量视频选择（用于视频信号转换的视频选择器） |
| 文件页数： | 8/10页 |
| 文件大小： | 134K |
| 代理商： | DG894 |
DG894
Vishay Siliconix
www.siliconix.com FaxBack 408-970-5600
5-8
Document Number: 70072
S-52433—Rev. D, 06-Sep-99
I
2
C Bus Operation—RGB Switching
Figure 6 shows an inexpensive RGB + stereo selector. The
two audio channels are switched via the C, Y terminals. The
CLC114 quad video buffer drives four 75- output lines.
Characteristics of the I C Bus
The I C Bus interface is ideally suited for communication
between different ICs or modules. Its salient features are:
Two wire bidirectional serial bus
–
Serial data (SDA) and serial clock (SCL) lines
Multi-master system (built-in arbitration for multi-master
systems)
Devices have independent clocks
Master and slave devices can be receivers and/or
transmitters.
Each device has a unique address.
Maximum bus clock rate of 100 kHz.
Any number of interfaces may be connected to the bus
–
Limited only by total capacitance of 400 pF
–
Each pin on bus limited to 10-pF capacitance
–
Input levels:
V
IL
max = 1.5 V (fixed supply operation)
V
IH
min = 3 V (fixed supply operation)
V
IL
max = 0.3 V
DD
(wide range supply operation)
V
IH
min = 0.7 V
DD
(wide range supply operation)
System Configuration
R
p
value depends on:
–
number of devices on bus
–
total bus capacitance
–
supply voltage (Figure 7).
Data Transfer on the I C Bus
If the bus is not being used, both SDA and SCL lines must be
left high.
Every byte put onto the SDA line should be eight bits long
(MSB first), followed by an acknowledge bit, which is
generated by the receiving device.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is
always the address byte. If this is the device’s own address,
the device will generate an acknowledge by pulling the SDA
line low during the ninth clock pulse, then accept the data in
subsequent bytes until another start or stop condition is
detected.
The eight bit of the address byte is the read/write bit (high =
read from addressed device, low = write to the addressed
device) so, for the DG894, the address is only considered valid
if the R/W bit is low.
Data bytes are always acknowledged during the ninth clock
pulse by the addressed device. Note that during the
acknowledge period the transmitting device must leave the
SDA line high.
Premature termination of the data transfer is allowed by
generating a stop condition at any time. When this happens,
the DG894 will remain in the state defined by the last complete
data byte transmitted.
R
p
R
p
Master
Transmitter/
Receiver
Master
Transmitter
Peripheral
Device
Peripheral
Device
SCL
SDA
FIGURE 7.
相关PDF资料 |
PDF描述 |
|---|---|
| DG894 | Component Video Selector |
| DG9051 | Precision 8-Ch/Dual 4-Ch/Triple 2-Ch Low Voltage Analog Switches/Multiplexers |
| DG9051DQ-T1-E3 | Precision 8-Ch/Dual 4-Ch/Triple 2-Ch Low Voltage Analog Switches/Multiplexers |
| DG9052 | Precision 8-Ch/Dual 4-Ch/Triple 2-Ch Low Voltage Analog Switches/Multiplexers |
| DG9052DQ-T1-E3 | Precision 8-Ch/Dual 4-Ch/Triple 2-Ch Low Voltage Analog Switches/Multiplexers |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DG894DJ | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Component Video Selector |
| DG894DW | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:Component Video Selector |
| DG9004X01XX-D4X WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DG9006X01XX-D4X WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| DG9010X01XX_D4X WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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