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参数资料
| 型号： | DK-CYCII-2C20N |
| 厂商： | Altera |
| 文件页数： | 3/21页 |
| 文件大小： | 0K |
| 描述： | CYCLONE II STARTER KIT EP2C20N |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Cyclone® II |
| 类型： | FPGA |
| 适用于相关产品： | Cyclone?II FPGAs |
| 所含物品： | 开发板、Quartus?II 网络版、Nios?II 网络版、缆线、附件、参考设计和演示 |
| 产品目录页面： | 605 (CN2011-ZH PDF) |
| 相关产品： | 544-2107-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2106-ND - IC CYCLONE II FPGA 20K 240-PQFP 544-2105-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2104-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-2103-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2102-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-2101-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1781-ND - IC CYCLONE II FPGA 20K 256-FBGA 544-1670-ND - IC CYCLONE II FPGA 20K 484-FBGA 544-1669-ND - IC CYCLONE II FPGA 20K 484-FBGA 更多... |
| 其它名称： | 544-1736 |
5
4
3
2
1
EP2S35
EP2C20
AUDIO
PAGE 4
D
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
I2C_SCLK
AUD_XCK
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
I2C_SCLK
AUD_XCK
AUD_ADCDAT
I2C_SDAT
AUD_ADCDAT
I2C_SDAT
AUD_ADCDAT
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
I2C_SDAT
I2C_SCLK
AUD_XCK
AUD_ADCDAT
AUD_BCLK
AUD_DACDAT
AUD_ADCLRCK
AUD_DACLRCK
I2C_SDAT
I2C_SCLK
AUD_XCK
24MHZ
DATA0
DCLK
ASDO
NCSO
NCE
24MHZ
DATA0
DCLK
ASDO
NCSO
NCE
PWR
PAGE 20
D
C
HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
VGA_R[0..3]
VGA_G[0..3]
VGA_B[0..3]
VGA_VSYNC
VGA_HSYNC
LED[0..17]
UART_TXD
DISPLAY
HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
VGA_R[0..3]
VGA_G[0..3]
VGA_B[0..3]
VGA_VSYNC
VGA_HSYNC
LED[0..17]
INPUT
UART_TXD
PAGE 5-6
IN/OUT
UART_RXD
UART_RXD
HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
VGA_R[0..3]
VGA_G[0..3]
VGA_B[0..3]
VGA_VSYNC
VGA_HSYNC
LED[0..17]
UART_RXD
UART_TXD
27MHZ
50MHZ
EXT_CLOCK
PS2_DAT
PS2_CLK
HEX0_D[0..6]
HEX1_D[0..6]
HEX2_D[0..6]
HEX3_D[0..6]
VGA_R[0..3]
VGA_G[0..3]
VGA_B[0..3]
VGA_VSYNC
VGA_HSYNC
LED[0..17]
UART_RXD
UART_TXD
27MHZ
50MHZ
EXT_CLOCK
PS2_DAT
PS2_CLK
NCONFIG
CONF_DONE
NSTATUS
TCK
TDI
TDO
TMS
LINK_D0
LINK_D1
LINK_D2
LINK_D3
NCONFIG
CONF_DONE
NSTATUS
TCK
TDI
TDO
TMS
LINK_D0
LINK_D1
LINK_D2
LINK_D3
DATA0
TDO
LINK_D3
USB BLASTER
DATA0
TDO
LINK_D3
PAGE 21
24MHZ
DCLK
ASDO
NCSO
NCE
NCONFIG
CONF_DONE
NSTATUS
TCK
TDI
TMS
LINK_D0
LINK_D1
LINK_D2
24MHZ
DCLK
ASDO
NCSO
NCE
NCONFIG
CONF_DONE
NSTATUS
TCK
TDI
TMS
LINK_D0
LINK_D1
LINK_D2
C
PS2_CLK
PS2_DAT
GPIO_B[0..35]
GPIO_B[36..71]
PS2_CLK
PS2_DAT
GPIO_B[0..35]
GPIO_B[36..71]
27MHZ
50MHZ
EXT_CLOCK
KEY[0..3]
SW[0..9]
27MHZ
50MHZ
EXT_CLOCK
KEY[0..3]
SW[0..9]
KEY[0..3]
SW[0..2]
SW[3..6]
SW[7..9]
GPIO_B[0..71]
KEY[0..3]
SW[0..2]
SW[3..6]
SW[7..9]
GPIO_B[0..71]
B
A
FLASH_RESET
FLASH_WE
FLASH_CE
FLASH_OE
FLASH_A[0..21]
DRAM_CLK
DRAM_CKE
DRAM_CS
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_LDQM
DRAM_UDQM
DRAM_BA0
DRAM_BA1
DRAM_A[0..11]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_LB
SRAM_UB
SRAM_A[0..17]
SD_CLK
SD_CMD
SD_DAT3
MEMORY
FLASH_RESET
FLASH_WE
FLASH_CE
FLASH_OE
FLASH_A[0..21]
DRAM_CLK
DRAM_CKE
DRAM_CS
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_LDQM
DRAM_UDQM
DRAM_BA0
DRAM_BA1
DRAM_A[0..11]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_LB
SRAM_UB
SRAM_A[0..17]
SD_CLK
SD_CMD
SD_DAT3
PAGE 18-19
FLASH_D[0..7]
DRAM_D[0..15]
SRAM_D[0..15]
SD_DAT
FLASH_D[0..7]
DRAM_D[0..15]
SRAM_D[0..15]
SD_DAT
FLASH_D[0..7]
FLASH_RESET
FLASH_WE
FLASH_CE
FLASH_OE
FLASH_A[0..21]
DRAM_D[0..15]
DRAM_CLK
DRAM_CKE
DRAM_CS
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_LDQM
DRAM_UDQM
DRAM_BA0
DRAM_BA1
DRAM_A[0..11]
SRAM_D[0..15]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_LB
SRAM_UB
SRAM_A[0..17]
SD_DAT
SD_CLK
SD_CMD
SD_DAT3
FLASH_D[0..7]
FLASH_RESET
FLASH_WE
FLASH_CE
FLASH_OE
FLASH_A[0..21]
DRAM_D[0..15]
DRAM_CLK
DRAM_CKE
DRAM_CS
DRAM_WE
DRAM_CAS
DRAM_RAS
DRAM_LDQM
DRAM_UDQM
DRAM_BA0
DRAM_BA1
DRAM_A[0..11]
SRAM_D[0..15]
SRAM_WE
SRAM_CE
SRAM_OE
SRAM_LB
SRAM_UB
SRAM_A[0..17]
SD_DAT
SD_CLK
SD_CMD
SD_DAT3
B
A
Title
Altera Cyclone II Starter Board
Size
B
Document Number
TOP LEVEL
Rev
1.1A
5
4
3
2
Date:
Tuesday, October 03, 2006
Sheet
1
3
of
21
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