参数资料
型号: DK-V6-BCCN-G-J
厂商: Xilinx Inc
文件页数: 2/11页
文件大小: 0K
描述: VIRTEX-6 FPGA CONNECTIVITY KIT
产品培训模块: Virtex-6 FPGA Overview
标准包装: 1
系列: Virtex® 6 LXT
类型: FPGA
适用于相关产品: Virtex? 6 LXT,XC6VLX240T
所含物品: 板,线缆,文档,软件 - 不包括电源 -
Virtex-6 Family Overview
DS150 (v2.4) January 19, 2012
Product Specification
10
Revision History
The following table shows the revision history for this document:
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maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
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Date
Version
Description of Revisions
02/02/09
1.0
Initial Xilinx release.
05/05/09
1.1
Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Table2, page3.
Updated the PCI Express design discussion on page 9 to remove the LogiCORE wrapper (<100 LUT)
description and clarify 8 lanes at the 5.0 Gb/s data rate. Clerical edits to Global Clock Lines and
10/100/1000 Mb/s Ethernet Controller (2,500 Mb/s Supported) sections. Overall clarifications made in
text.
06/24/09
1.2
Added ordering information and FPGA documentation sections.
09/16/09
2.0
Added Virtex-6 HXT family information. Updated number to 26 Mb in Configuration section.
11/06/09
2.1
Clarified distributed RAM features on page 1. Updated CLB slice number for the XC6VHX565T in
Table 1. Updated compliance to the PCI Express Base Specification Revision 2.0. Updated Integrated
Interface Blocks for PCI Express Designs section with link to documentation.
01/28/10
2.2
In Table 1, there are two Ethernet MACs in the XC6VHX255T. Under Clock Management, page 5,
revised the VCO frequency minimum to 600 MHz which also revised the phase-shift timing increment.
Updated GTX transceivers operating data rate range to 6.6 Gb/s. Changed GTX PLL input reference
clock frequency divider.
03/24/11
2.3
Changed document classification to Preliminary Product Specification from Advance Product
Specification. Updated Figure 1.
01/19/12
2.4
Changed document classification to Product Specification from Preliminary Product Specification.
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