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| 型号： | DK-V6-EMBD-G |
| 厂商： | Xilinx Inc |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | EMBEDDED KIT |
| 产品培训模块： | Virtex-6 FPGA Overview |
| 标准包装： | 1 |
| 系列： | Virtex® 6 |
| 类型： | FPGA |
| 适用于相关产品： | Virtex? 6 LXT，XC6VLX240T |
| 所含物品： | 板，线缆，文档，电源，软件 |
| 其它名称： | Q5267241 |
Spartan-6 Family Overview
DS160 (v2.0) October 25, 2011
Product Specification
5
Clock Management
Each Spartan-6 FPGA has up to six CMTs, each consisting of two DCMs and one PLL, which can be used individually or
cascaded.
DCM
The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, and 270° (CLK0, CLK90, CLK180, and
CLK270). It also provides a doubled frequency CLK2X and its complement CLK2X180. The CLKDV output provides a
fractional clock frequency that can be phase-aligned to CLK0. The fraction is programmable as every integer from 2 to 16,
as well as 1.5, 2.5, 3.5 . . . 7.5. CLKIN can optionally be divided by 2. The DCM can be a zero-delay clock buffer when a clock
signal drives CLKIN, while the CLK0 output is fed back to the CLKFB input.
Frequency Synthesis
Independent of the basic DCM functionality, the frequency synthesis outputs CLKFX and CLKFX180 can be programmed to
generate any output frequency that is the DCM input frequency (FIN) multiplied by M and simultaneously divided by D, where
M can be any integer from 2 to 32 and D can be any integer from 1 to 32.
Phase Shifting
With CLK0 connected to CLKFB, all nine CLK outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, and CLKFX180) can be shifted by a common amount, defined as any integer multiple of a fixed delay. A fixed DCM
delay value (fraction of the input period) can be established by configuration and can also be incremented or decremented
dynamically.
Spread-Spectrum Clocking
The DCM can accept and track typical spread-spectrum clock inputs, provided they abide by the input clock specifications
listed in the Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. Spartan-6 FPGAs can generate a spread-
spectrum clock source from a standard fixed-frequency oscillator.
PLL
The PLL can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks in
conjunction with the DCMs. The heart of the PLL is a voltage-controlled oscillator (VCO) with a frequency range of
400 MHz to 1,080 MHz, thus spanning more than one octave. Three sets of programmable frequency dividers (D, M, and O)
adapt the VCO to the required application.
The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL
phase comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides the VCO
output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the
VCO within its controllable frequency range.
The VCO has eight equally spaced outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive
one of the six output dividers, O0 to O5 (each programmable by configuration to divide by any integer from 1 to 128).
Clock Distribution
Each Spartan-6 FPGA provides abundant clock lines to address the different clocking requirements of high fanout, short
propagation delay, and extremely low skew.
Global Clock Lines
In each Spartan-6 FPGA, 16 global-clock lines have the highest fanout and can reach every flip-flop clock. Global clock lines
must be driven by global clock buffers, which can also perform glitchless clock multiplexing and the clock enable function.
Global clocks are often driven from the CMTs, which can completely eliminate the basic clock distribution delay.
I/O Clocks
I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer
(SERDES) circuits, as described in the I/O Logic section.
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| DK-V6-EMBD-G-XP1 | 功能描述:DEV KIT EMBEDDED VIRTEX 6 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Virtex® 6 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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| DK-V7-VC709-CES-G-J | 制造商:Xilinx 功能描述:KIT V7 VC709 CONNECT ES |
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