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参数资料
| 型号： | DLX2416 |
| 厂商： | Osram Opto Semiconductors GmbH |
| 英文描述： | Intelligent Display Device |
| 中文描述： | 智能显示装置 |
| 文件页数： | 5/5页 |
| 文件大小： | 213K |
| 代理商： | DLX2416 |
www.in
fi
neon.com/opto
1-888-In
fi
neon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG
Regensburg, Germany
www.osram-os.com
+49-941-202-7178
2000 In
fi
neon Technologies Corp.
Optoelectronics Division
San Jose, CA
Appnote 14
5
May 31, 2000-12
Interfacing the DLX2416
A general and straightforward interface circuit is shown
in Figure 6. This scheme can easily interface to μP sys-
tems or any other systems which can provide the
seven data lines, appropriate address and control lines
Parallel I/O
The parallel I/O device of a microprocessor can easily
be connected to the circuit in Figure 6. One eight bit
output port can provide the seven input data bits and
the cursor (CU). Another eight bit output port can con-
tain the address and chip enable information and the
other control signals.
Figure 7 illustrates a 16-character display with an 8080
system using the 8255 programmable peripheral inter-
face I/O device. The following program will display a
simple 16-character message using this interface.
I/O or Memory Mapped Addressing
Some designers may wish to avoid the additional cost
of a parallel I/O in their system. Structuring the address-
ing architecture for the DLX2416 to look like a set of
peripheral or output devices (I/O mapped) or RAM’s and
ROM’s (memory mapped) is very easy. Figure 8 shows
the simplicity of interfacing to microprocessors, such
as 8080, Z80 and 6502 as examples.
The interface with the 6800 microprocessor in Figure 9
illustrates the need for designers to check the timing
requirements of the DLX2416 and the μP. The typical
data output hold time is only 30 ns for DBE=
two inverters in the DBE line are added to increase the
data output hold time for compatibility with the 50 nS
minimum spec of the DLX2416.
2 timing;
Conclusion
Although other manufacturers’ products are used in
examples, this application note does not imply specific
endorsement, or recommendation or warranty of other
manufacturers’ products by Infineon / OSRAM.
The interface schemes shown demonstrate the sim-
plicity of using the DLX2416 with microprocessors. The
slight differences encountered with various micropro-
cessors to interface with the DLX2416 are similar to
those encountered when using different RAMs. The
techniques used in the examples were shown for their
generality. The user will undoubtedly invent other
schemes to optimize his particular system to its
requirements.
Figure 8. Mapped interface
Figure 9. 6800 microprocessor interface
Address
Display
Select
Decoder
Parallel
I/0 Device
Optional
Buffers
Reset
Int
Hold
Wait
Display Display Display Display
D15
8980
Z80
6502
D0
OSC
A0
A1
A2
A3
Data 0-6
Data
Control
CUE
CLR
BL
WR
Address
Data
Control
Data
Address
DBE
Decoder
6820
PIA
CUE
BL
CLR
Data
Address
H1
H2
0
1
0
2
Clock
Driver
6800
BA
VMA
R/W
CE CE
Reset
NMI
Halt
IRQ
TSC
A0
–
A1
D0
–
D7
Display
Display
Display
Display
Data
D15
D0
W
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