参数资料
型号: DP83848YB/NOPB
厂商: National Semiconductor
文件页数: 55/86页
文件大小: 0K
描述: IC TXRX ETHERNET PHYTERA 48-LQFP
标准包装: 250
类型: 收发器
驱动器/接收器数: 1/1
规程: 以太网
电源电压: 3 V ~ 3.6 V
安装类型: 表面贴装
封装/外壳: 48-LQFP 裸露焊盘
供应商设备封装: 48-LQFP 裸露焊盘(7x7)
包装: 带卷 (TR)
其它名称: DP83848YBTR
www.national.com
58
D
P
83
848
YB
7.2.10 10Base-T Status/Control Register (10BTSCR)
6
5
LED_CNFG[1]
LED_CNFG[0]
0, RW
Strap, RW
LEDs Configuration
LED_CNFG[1]
LED_ CNFG[0]
Mode Description
Don’t care
1
Mode 1
0
Mode 2
10
Mode 3
In Mode 1, LEDs are configured as follows:
LED_LINK = ON for Good Link, OFF for No Link
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Activity, OFF for No Activity
In Mode 2, LEDs are configured as follows:
LED_LINK = ON for good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Collision, OFF for No Collision
Full Duplex, OFF for Half Duplex
In Mode 3, LEDs are configured as follows:
LED_LINK = ON for Good Link, BLINK for Activity
LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s
LED_ACT/COL = ON for Full Duplex, OFF for Half Duplex
4:0
PHYADDR[4:0]
Strap, RW
PHY Address: PHY address for port.
Table 30. 10Base-T Status/Control Register (10BTSCR), address 0x1A
Bit
Bit Name
Default
Description
15
10BT_SERIAL
Strap, RW
10Base-T Serial Mode (SNI)
1 = Enables 10Base-T Serial Mode
0 = Normal Operation
Places 10 Mb/s transmit and receive functions in Serial Network
Interface (SNI) Mode of operation. Has no effect on 100 Mb/s
operation.
14:12
RESERVED
0, RW
RESERVED:
Must be zero.
11:9
SQUELCH
100, RW
Squelch Configuration:
Used to set the Squelch ‘ON’ threshold for the receiver.
Default Squelch ON is 330mV peak.
8
LOOPBACK_10_D
IS
0, RW
In half-duplex mode, default 10BASE-T operation loops Transmit
data to the Receive data in addition to transmitting the data on the
physical medium. This is for consistency with earlier 10BASE2 and
10BASE5 implementations which used a shared medium. Setting
this bit disables the loopback function.
This bit does not affect loopback due to setting BMCR[14].
Table 29. PHY Control Register (PHYCR), address 0x19 (Continued)
Bit
Bit Name
Default
Description
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