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参数资料
| 型号： | DPSD32ME8TKY5-DP-XX75P2 |
| 元件分类： | DRAM |
| 英文描述： | 32M X 8 SYNCHRONOUS DRAM MODULE, PDSO54 |
| 封装： | STACKED, TSOP2-54 |
| 文件页数： | 2/2页 |
| 文件大小： | 140K |
| 代理商： | DPSD32ME8TKY5-DP-XX75P2 |
MECHANICAL DIAGRAM
.020 [.51]
.0315 [.80]
TOP VIEW
SIDE VIEW
BOTTOM VIEW
END VIEW
PIN 1
INDEX
.502±.008
.891 MAX.
[12.75±.20]
[22.63 MAX.]
.102 MAX. [2.59 MAX]
Lead Toe-to-Toe per device datasheet
Inch [mm]
END VIEW DETAIL
.463 [11.76] TYP
COPLANARITY:
.004 [.10] from seating plane
TYP.
30A226-01
REV. B 6/03
2
DPAC Technologies Products & Services for the Integration Age
7321 Lincoln Way, Garden Grove, CA 92841 Tel 714 898 0007 Fax 714 897 1772
www.dpactech.com Nasdaq: DPAC
2003 DPAC Technologies, all rights reserved. DPAC Technologies, DuraStack, Memory Stack, LP-Stack, CS-Stack are trademarks of DPAC Technologies Corp.
DPSD32ME8TKY5
256 Megabit Synchronous DRAM
* Contact your sales representative for supplier and manufacturer codes.
NOTE:
1. AC Parameters of base memory are unchanged from device manufacturers’ specifications.
2. DC Parameters may be affected by stacking. Please refer to application note 53A004-00 for further information.
3. For assembly and inspection procedures, refer to application note 53A001-00.
4. Maximum reflow temperature recommendation is 215°C.
ORDERING INFORMATION
DP
-
PREFIX
SD 32M
E
8
Y5
PACKAGE
MEMORY
DESIG
MEMORY
TYPE
MODULE WITH DUAL CLOCK ENABLES
DEPTH
WIDTH
DESIG
TK
STACKABLE TSOP
SYNCHRONOUS DRAM
SUPPLIER
-DP
SUPPLIER CODE *
128 MEGABIT LVTTL BASED
MFR ID
XX
REVISION
MEMORY
X
BLANK
REVISION NOT SPECIFIED
PER MANUFACTURER DIE REVISION
MANUFACTURER CODE *
n
70P2
75P2
75
55
60
70
TIME
XXX
CYCLE
10
08
12
P12
P13
7.5ns (133MHz) CL3
5.5ns (183MHz) CL3
7ns (143MHz) CL3
6ns (166MHz) CL2
7ns (133MHz) CL2
7.5ns (133MHz) CL2
PC100 / CL2
12ns (83MHz)
8ns (125MHz)
10ns (100MHz)
PC100 / CL3
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| DPSD32ME8TKY5-DP-XX75 | 32M X 8 SYNCHRONOUS DRAM MODULE, PDSO54 |
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