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参数资料
| 型号： | DS-11802D4-103Z |
| 英文描述： | Converter |
| 中文描述： | 转换器 |
| 文件页数： | 7/7页 |
| 文件大小： | 226K |
| 代理商： | DS-11802D4-103Z |
DS1200
7 of 7
AC ELECTRICAL CHARACTERISTICS
(0C to +70C; VCC = 5V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Data to CLK Setup
tDC
35
ns
3, 9
Data to CLK Hold
tCDH
40
ns
3, 9
Data to CLK Delay
tCDD
125
ns
3, 4, 6, 9
CLK Low Time
tCL
125
ns
3, 9
CLK High Time
tCH
125
ns
3, 9
CLK Frequency
fCLK
DC
4.0
MHz
3, 9
CLK Rise and Fall
tR, tF
500
ns
9
RST
to Clock Setup
tCC
1s
3, 9
CLK to RST Hold
tCCH
40
ns
3, 9
RST
Inactive Time
tCWH
125
ns
3, 9, 14
RST
to I/O High-Z
tCDZ
50
ns
3, 9
NOTES:
1) All voltages and resistances are referenced to ground.
2) Input levels apply to CLK, DQ, and RST while VCC is not connected to the tag, then RST input
reverts to VIHE.
3) Measured at VIH = 2.0 or VIL = 0.8V and 10ns maximum rise and fall time.
4) Measured at VOH = 2.4V and VOL = 0.4V.
5) For CLK, DQ, RST , and VCC at 5V.
6) Load capacitance = 50pF.
7) Applies to RST when VCC < 3.8V.
8) Measured with outputs open.
9) Measured at VIH of RST greater than or equal to 3.8V when RST supplies power.
10) Logic 1 maximum is VCC + 0.3V if the VCC pin supplies power and RST +0.3V if the RST pin
supplies power.
11) RST logic 1 maximum is VCC + 0.3V if the VCC pin supplies power and 5.5V maximum if RST
supplies power.
12) Each DS1200 is marked with a four-digit date code AABB. AA designates the year of manufacture.
BB designates the week of manufacture. The expected tDR is defined as starting at the date of
manufacture.
13) Average AC RST current can be determined using the following formula:
ITOTAL = 2 + ILOAD DC + (4 x 10
-3)(CL + 140)f
ITOTAL and ILOAD are in mA; CL is in pF; f is in MHz.
Applying the above formula, a load capacitance of 50pF running at a frequency of 4.0MHz gives an
ITOTAL current of 5mA.
14) When RST is supplying power, tCWH must be increased to 100ms.
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