参数资料
型号: DS1005-200+
厂商: Maxim Integrated Products
文件页数: 4/6页
文件大小: 0K
描述: IC DELAY LINE 5TAP 200NS 14-DIP
标准包装: 25
标片/步级数: 5
功能: 不可编程
延迟到第一抽头: 40ns
接头增量: 40ns
可用的总延迟: 200ns
独立延迟数: 1
电源电压: 4.75 V ~ 5.25 V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 14-DIP(0.300",7.62mm)
供应商设备封装: 14-PDIP
包装: 管件
DS1005
4 of 6
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25
°C. Delays accurate on both rising and falling edges within ±2 ns or ±3%, whichever
is greater.
4. See Test Conditions.
5. The combination of temperature variations from 25
°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of
±1.5 ns or
±4%, whichever is greater.
6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows
down, all other taps will also slow down; TAP 3 can never be faster than TAP 2.
7. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-
sensitive (decoupling, layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
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