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参数资料
| 型号： | DS1013G-55 |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | Delay Line |
| 英文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| 封装： | 0.300 INCH, PLASTIC, MS-001AC, DIP-14 |
| 文件页数： | 19/23页 |
| 文件大小： | 5292K |
| 代理商： | DS1013G-55 |
DS1013
5 of 6
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns for -10 to -60, ±3%
for -70 to 100 and ±5% for -150 and longer delays.
4. See “Test Conditions” section.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations
from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional delay shift of ±1.5 ns or ±3%,
whichever is greater.
6. All output delays tend to vary unidirectionally over temperature or voltage ranges (i.e., if OUT 1
slows down, all other outputs also slow down).
7. Period specifications may be exceeded; however, accuracy will be application-sensitive (decoupling,
layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
相关PDF资料 |
PDF描述 |
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| DS1013S-55 | SILICON DELAY LINE, TRUE OUTPUT, PDSO16 |
| DS1013G-30 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
| DS1013M-65 | SILICON DELAY LINE, TRUE OUTPUT, PDIP8 |
| DS1013H-10 | SILICON DELAY LINE, TRUE OUTPUT, PDIP8 |
| DS1013K-55 | SILICON DELAY LINE, TRUE OUTPUT, PDIP14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1013G-60 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Tapped Delay Line |
| DS1013G-65 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Tapped Delay Line |
| DS1013G-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Tapped Delay Line |
| DS1013G-75 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Tapped Delay Line |
| DS1013G-80 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Tapped Delay Line |
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