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参数资料
| 型号： | DS1020S-50/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 8/9页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 256TAP 16-SOIC |
| 标准包装： | 1,000 |
| 标片/步级数： | 256 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 10ns |
| 接头增量： | 0.5ns |
| 可用的总延迟： | 137.5ns |
| 独立延迟数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
DS1020
8 of 9
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of the output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
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| DS1020S-15/T&R | IC DELAY LINE 256TAP 16-SOIC |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1021 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Programmable 8-Bit Silicon Delay Line |
| DS1021-25 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Programmable 8-Bit Silicon Delay Line |
| DS1021-50 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Programmable 8-Bit Silicon Delay Line |
| DS1021S-25 | 功能描述:延迟线/计时元素 RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| DS1021S-25/T&R | 制造商:Maxim Integrated Products 功能描述:IC DEL LN 256TAP 73.75NS 16SOIC |
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